Abstract: A method for fabricating semiconductor devices with a self-spaced contact is provided. Spacing required between the self-spaced contact and a gate region is lessened, thus reducing chip size, and parasitic capacitance and resistance. A transistor region includes a gate and diffusion region. A pad oxide layer comprises an uppermost layer of the gate. A spacer oxide is formed on side walls of the gate region. The thickness of the pad oxide layer controls the width of the spacer oxide region. The spacer oxide insulates the gate from the diffusion regions, so that electrical contacts may be formed close to the gate for reducing the overall size of the semiconductor device. The doping structure of the diffusion regions is controlled by the width of the spacer oxide regions. Thus, the doping structure of the diffusions can be altered to reduce parasitic capacitance and resistance.

Abstract: A method and an electrically conductive interconnect structure (30) for controlling electromigration. The electrically conductive interconnect structure (30) comprises a groove (33) adjacent an electrically conductive interconnect (39). The electrically conductive interconnect (39) is patterned from a deposited layer of conductive material which contains global grain microstructures. Moreover, the electrically conductive interconnect (39) is patterned to have polycrystalline and single-grain segment lengths that are less than a length at which an electromigration flux fails to overcome a gradient-driven counter flux in a line segment. The groove (33) controls the polycrystalline and single-grain segment lengths to be less than the critical length, thereby reducing electromigration.

Abstract: In a method for manufacturing tunnel-effect sensors, a tip (2) composed of the silicon of the substrate (1) is produced on a substrate (1) of silicon with electrically conductively doped regions (4) by oxidation of the silicon using a nitride mask on the surface. Using the planarized oxide layer (5) produced in the oxidation step, a beam (3) of polysilicon that is anchored on the substrate (1) is applied, for example, over the tip (2) as a cooperating electrodes for the utilization of the tunnel effect and is electrically conductively doped. Subsequently, the oxide layer (5) is removed.

Abstract: In a method of planarizing a semiconductor wafer having aluminum interconnect tracks formed thereon, a method is disclosed for applying inorganic spin-on glass which comprises applying the spin-on glass to the wafer in a coating and spinning chamber in a moisture-free environment, transferring the wafer in a moisture-free environment to a curing station, curing the spin-on glass at a temperature in the range of about 80.degree. to 250.degree. C. in the moisture-free environment at the curing station, and returning the wafers to the coating and spinning chamber. The above steps are repeated until a sufficient film thickness has been achieved without in the interim exposing the wafer to moisture conditions such that reverse hydrolysis si minimized during the planarization process. In this way crack-free inorganic SOG films can be produced.

Abstract: A process for the preparation of a thin film transistor is provided which includes sequentially depositing a gate insulating layer, an amorphous silicon layer, and an n+ amorphous silicon layer. The n+ amorphous silicon layer is disposed between source and drain electrodes and is oxidized by a plasma oxidation process so that switching properties, interface properties between the amorphous silicon layer and the n+ amorphous silicon layer and a production yield are enhanced, while the preparation steps of forming an etch stopper and removing the n+ amorphous silicon layer disposed between the source electrode and the drain electrode are reduced.

Abstract: A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well.

Abstract: To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower.

Abstract: An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).

Abstract: Disclosed herein is abrasives consisting of fine particles of fluorinated silicon oxide which do not contain alkali metal and methods of thier manufacture, and high yield and high reliability methods of manufacturing semiconductor devices by the use of these abrasives. The abrasive comprises a solution in which fine particles of fluorinated silicon oxide are dispersed is formed by addition of boric acid to an aqueous solution of hydrosilicofluoric acid or addition of pure water to an alcohol solution of alkoxyfluorosilane. By the use of these abrasives, a layer insulating film for multi-layer wiring can be flattened.

Abstract: A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

Abstract: A method for fabricating an LCD-TFT, which can prevent degradation of image quality of a liquid crystal display by preventing blackening of the pixel electrode due to H.sub.2 plasma at the time of deposition of a protective insulation film. The method includes the steps of forming a gate electrode on a transparent glass substrate, and forming a gate insulation film, a semiconductor layer, and an impurity doped semiconductor layer successively over the surface of the substrate. The semiconductor layer and the impurity doped semiconductor layer are patterned, leaving layers only over a part of the gate insulation film over the gate electrode. A pixel electrode is formed on a part of the gate insulation film offset from the gate electrode. A metal barrier layer and source/drain electrodes are over the surface of the substrate.

Abstract: Body portions (36) of semiconductor crystalline silicon material of sufficient quality to form high-mobility TFTs (thin-film transistors) and other semiconductor devices of a driver circuit are formed by depositing on a substrate (14) a layer of insulating silicon-based non-stoichiometric compound material (32) and then converting this material (32) into the semiconductive crystalline material (36) by heating with an energy beam (40), for example from an excimer laser. The use of an energy beam (40) permits easy localization of the heating (and consequent conversion) both vertically and laterally. The deposition (e.g. by plasma-enhanced chemical vapour deposition) and the beam annealing can both be carried out without heating the substrate (14) to high temperatures, and so a glass or other low-cost substrate (14) can be used. An unconverted part (32a) underlying the crystalline silicon body portion (36) can form at least part of a gate insulator of the TFT.

Abstract: A dielectric film is formed on a P type silicon substrate. Then a specified resist pattern is formed on the dielectric film. Using this resist pattern as the mask, a phosphorus ion beam is implanted. Then, removing the resist pattern, heat treatment is given. By this heat treatment, a photo diode is formed in a depth of about 1 .mu.m. A specified resist pattern is formed again on the dielectric film. Using this resist pattern as the mask, boron ions are implanted. Thus, a channel stopper region is formed. Afterwards, removing the resist pattern, the dielectric film is removed. Again, a dielectric film is formed on the silicon substrate. Later, a stacked oxide film is formed in the other regions than the region for forming the photo diode on the dielectric film. Using the stacked oxide film as the mask, a boron ion beam is implanted.

Abstract: A method for fabricating a TFT-LCD which enables point defects such as electrical short circuits between a pixel and a thin film transistor or between a bus line and a pixel to be repaired during fabrication.

Abstract: A method for making gate dielectrics for MOS devices includes first forming a silicon oxynitride layer, and then forming a silicon dioxide layer that underlies the oxynitride layer. The oxynitride layer functions as a membrane for controlled diffusion of oxygen to the oxidation region of the silicon substrate.

Abstract: The process for making a matrix of thin layer transistors with memory capacitors includes forming a first conductive layer on a substrate, and in a first mask step, etching it to form row conductors of the matrix, gate contacts of the thin layer transistors and ground electrodes of the memory capacitors; forming a gate-insulating layer for the thin layer transistors; forming a semiconductor layer, especially an a-Si:H semiconductor layer; applying a p- or n-doped semiconductor layer to provide drain and source contacts; forming and etching a second conductive layer for the column conductors of the matrix of the thin layer transistors, the drain and source contacts of the thin layer transistors and the counter electrodes of the memory capacitors in a second mask step; plasma etching of the doped semiconductor layer with the second conductor layer acting as mask and determining an end of the etching process by observing the optical emission of an etching plasma used for the plasma etching; etching the undoped s

Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.

Abstract: A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure.

Abstract: A high voltage silicon carbide MESFET includes an electric field equalizing region in a monocrystalline silicon carbide substrate at a face thereof, which extends between the drain and gate of the MESFET and between the source and gate of the MESFET. The region equalizes the electric field between the drain and gate and between the source and gate to thereby increase the breakdown voltage of the silicon carbide MESFET. The first and second electric field equalizing regions are preferably amorphous silicon carbide regions in the monocrystalline silicon carbide substrate. The amorphous regions are preferably formed by performing a shallow ion implantation of electrically inactive ions such as argon, using the source and drain electrodes and the metal gate as a mask, at a sufficient dose and energy to amorphize the substrate face. A third amorphous silicon carbide region may be formed at the face, adjacent and surrounding the MESFET to provide edge termination and isolation of the MESFET.

Abstract: A liquid crystal image display device comprising an insulating substrate having plural scanning lines and signal lines and a switching device and a pixel electrode provided for each of pixels, a light-transmissive insulating substrate having a transparent conductive counter electrode and liquid crystal filled between both substrates, wherein said signal lines or scanning lines for supplying electric signals to said switching devices and conductive paths for connecting said switching devices with the pixel electrodes are coated with an thick organic film so as to be electrically isolated from said liquid crystal.