Abstract: A method for fabricating a contact plug capable of achieving a smooth tungsten growth by implanting silicon ions in the bottom surface of a via contact hole not only to remove a polymer formed on the bottom surface of the via contact hole, but also to provide a seed layer for the tungsten growth, and capable of preventing an adverse effect on the contact resistance resulting from a formation of AlF.sub.3 due to a direct contact between Al and WF.sub.6.

Abstract: Method for producing a silicon technology transistor on a nonconductor. This method consists in particular of forming a thin film of silicon (6) on a nonconductor (4) and then a mask (8, 10) including one opening (13) at the location provided for the channel (26) of the transistor; of locally oxidizing (14) the unmasked silicon to form an oxidation film; of eliminating the mask; of forming source (18) and drain (20) regions in the silicon by ion implantation with the oxidation film being used to mask this implantation; of eliminating the oxidation film; and of forming a thin gate nonconductor between the source and the drain and then forming the gate.

Abstract: Using a gate electrode formed on a semiconductor film as a mask, impurity ions are implanted into the semiconductor film. Thereafter, a photoresist film is formed on the substrate including the gate electrode. The photoresist film on the gate electrode is then exposed to light from a back side of the gate electrode. By this self-alignment method, a resist pattern narrower than the gate electrode is formed. Then, the gate electrode is narrowed through the etching thereof using the photoresist pattern as a mask, whereby an offset gate structure of a thin-film transistor is obtained.

Abstract: A polycrystalline silicon film pattern 3 having a thickness of below 120 nm is formed on a silicon oxide film 2 provided on the principal surface of a silicon substrate 1. The polycrystalline silicon film pattern 3 is covered with a boron silicate glass film 4. By heat treatment, boron is diffused from the boron silicate glass film 4 to the polycrystalline silicon film pattern 3 to form a polycrystalline silicon resistance element 5 containing boron at a density of above 1.times.10.sup.19 atoms/cm.sup.3. As a result, the temperature coefficient of the resistance element 5 comprising the polycrystalline film can be reduced.

Abstract: An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.

Abstract: A thin-film transistor panel is constituted by forming, on an insulating substrate, a plurality of thin-film transistors, a plurality of gate lines for each connecting gate electrodes of the thin-film transistors, and a plurality of pixel electrodes formed of a transparent conductive film connected to the thin-film transistors, then forming a low-resistance metal film of an Al or Al alloy for a data line and a surface metal film of Cr with a high density, forming a photoresist film of a predetermined pattern on the surface metal film, and etching the data line metal film and surface metal film. Then, the surface metal film remaining on the data line metal film is eliminated.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: FET devices according to the invention are made by etching separation grooves and the via-holes from the front surface of the substrate. Thereafter, the thickness of the substrate is reduced from the rear surface to expose the plating in the via-holes and separation grooves. A rear surface electrode and a plated heat sink are sequentially deposited on the rear surface of the thinned substrate. The devices are divided from a wafer by etching and/or severing along the separation grooves and at opposed locations along the plated heat sink.

Abstract: Improved N-channel and P-channel field effect transistor device structure having self-aligned polysilicon pads contacts and a process for making such devices has been achieved. The doped polysilicon pad contact are formed over the source/drain areas of the field effect transistors and are used to form shallow self-aligned diffused contact to the source/drain areas. These polysilicon pads provide a low resistance ohmic contacts that are free from implant damage that would otherwise cause increased junction leakage current and are free of metal spiking at the source/drain area perimeter that would cause metal contact to substrate shorts. The increased area of the polysilicon pads over the source/drain area allows for relaxed design ground rule for the contact openings, making for a more manufacturable process for Ultra Large Scale Integration applications.

Abstract: A method for fabricating a thin film transistor which includes steps for, forming a first and a second gate electrode on a transparent insulation substrate, forming a gate insulation film on the exposed surface and forming an active layer on a surface of the gate insulation film overlying the first gate electrode, forming a transparent conductive material pattern on a surface of the active layer overlying the first gate electrode and a pixel electrode on the surface of the gate insulation film extending laterally from the surface of the second gate electrode toward the active layer, forming a source electrode over the surfaces of the active layer and a drain electrode which extends from the other side of the transparent conductive material across the active layer to the surface of one side of the pixel leaving space between the source electrode and the drain electrode, an ohmic contact semiconductor layer automatically formed beneath the source electrode and the drain electrode, removing the exposed semicondu

Abstract: A process for fabricating an IGFET integrated circuit having two gate dielectric layers with different parameters is provided. Typically, the process is used for fabrication of dual voltage CMOS integrated circuits. The integrated circuit may include high voltage transistors having a first gate dielectric thickness and low voltage transistors having a second gate dielectric thickness. A first gate dielectric layer and a first gate layer for the high voltage transistors are formed over active regions of a substrate. The device is patterned to expose low voltage transistor areas, and the first gate dielectric layer and the first gate layer are removed in the low voltage transistor areas. Then, a second gate dielectric layer and a second gate layer for the low voltage transistors are formed on the device. The device is patterned to expose the high voltage transistor areas, and the second gate dielectric layer and the second gate layer are removed in the high voltage transistor areas.

Abstract: A method for manufacturing a TFT of a SRAM in a highly-integrated semiconductor device, to enlarge the grain size of a polysilicon film, includes steps of depositing amorphous silicon film under a pressure capable of maintaining a uniform thickness thereof, and forming a polysilicon film which has a maximized grain size in the same tube that the amorphous silicon film has been deposited, while performing an annealing process by raising the temperature to 600.degree.-650.degree. C. for 4-10 hours under the pressure which is lowered to approximately 10.sup.-3 Torr. The polysilicon film having a maximized grain size is utilized as the channels of the TFT.

Abstract: A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source and drain junction under the gate electrode but does not increase substantially the junction capacitance under the source and drain contacts, thereby improving punch-through characteristic while maintaining device performance.

Abstract: A method for the fabrication of semiconductor device includes the steps of forming a first wiring layer on an insulating film overlaying a semiconductor substrate, depositing an interlayer insulating film entirely on the first wiring layer, etching the interlayer insulating film selectively to form a contact hole exposing the first wiring layer therethrough, forming a metal film on the interlayer insulating film and in the contact hole, etching the metal film selectively to leave the metal film only around the contact hole, depositing a mid-insulating film on the remaining metal film and on the interlayer insulating film applying annealing to the metal film to form a metal plug in the contact hole, the metal film filling the contact hole, removing the mid-insulating film and forming a second wiring layer on the interlayer insulating film and on the metal plug.

Abstract: This invention relates to a method for fabrication of MOS transistors having LDD(Lightly Doped Drain) structure which comprises the steps of forming a gate insulation film on a semiconductor substrate of a first conduction type, forming a conduction layer for forming a gate pole on the gate insulation film, forming an oxidation prevention layer on the conduction layer, carrying out selective etchings of the oxidation prevention layer and the conduction layer to a certain thicknesses of areas except the gate pole area, forming an oxide film by an oxidation of the exposed portion of the conduction layer, carrying out a selective etching of the oxide film by using the oxidation prevention layer as a mask, forming a high density impurity area of a second conduction type in a predetermined area of the semiconductor substrate by a high density ion injection of the second conduction type impurity, removing the oxidation prevention layer and the oxide film, forming a low density impurity area of the second conduction

Abstract: Method of fabricating a semiconductor device, such as a thin-film transistor, having improved characteristics and improved reliability. The method is initiated with formation of a thin amorphous silicon film on a substrate. A metallization layer containing at least one of nickel, iron, cobalt, and platinum is selectively formed on or under the amorphous silicon film so as to be in intimate contact with the silicon film, or these metal elements are added to the amorphous silicon film. The amorphous silicon film is thermally annealed to crystallize it. The surface of the obtained crystalline silicon film is etched to a depth of 20 to 200.ANG., thus producing a clean surface. An insulating film is formed on the clean surface by CVD or physical vapor deposition. Gate electrodes are formed on the insulating film.

Abstract: A silicon on insulator integrated circuit device is provided which comprises a substrate (10), a buried oxide layer (12), and an outer silicon layer (14). A buried (p)-layer (16) and a buried (n)-well region (26) are formed in order to position (p)-(n) junctions beneath (n)-channel and (p)-channel devices respectively formed in the outer silicon layer (14) outwardly from the (p)-layer (16) and (n)-well (26).

Abstract: A method for making an integrated circuit characterized by: determining a range of bonding pad pitches which varies between a minimum bonding pad pitch and a maximum bonding pad pitch; setting a driver pitch to the minimum bonding pad pitch; forming a base set including a plurality of drivers having the determined driver pitch; forming customization layers over the base set, where the customization layers include a plurality of bonding pads having a pad pitch greater than the minimum bonding pad pitch but less than or equal to the maximum bonding pad pitch; and coupling some, but not all, of the drivers to the pads. As a result, a single base set can be used to make integrated circuits having a range of bonding pad pitches. The method and structure of the present invention are very well adapted for use in gate array integrated circuits.

Abstract: An amorphous silicon hydride thin film is deposited on an insulating body by a plasma CVD method, and is then heated for dehydrogenating the amorphous silicon thin film so that a dehydrogenated amorphous silicon thin film containing hydrogen of 3 atomic % or less is formed. The insulating body may be an insulating substrate (such as a glass substrate) alone, or a combination of an insulating substrate with an intermediate insulating base layer thereon. Impurity ions are injected into the dehydrogenated amorphous silicon hydride thin film to form source and drain regions. Excimer laser beams are applied to the dehydrogenated amorphous silicon thin film, thereby polycrystallizing the amorphous silicon thin film into a polysilicon thin film and activating the injected impurity ions.

Abstract: A TFT panel is manufactured by a process of forming an oxide voltage-apply lines, gate lines, and capacitor lines on an insulating substrate, and a process of forming thin-film transistors, pixel electrodes, data lines, and ground lines. In a state that one end of the gate line and both ends of the capacitor line are connected to the oxide voltage-apply line, oxide films are formed on the surfaces of the gate line and the capacitor line by anodization. After forming the oxide film, the gate line and the capacitor line are electrically separated from the oxide voltage-apply line.