Abstract: Methods for generating quantum computing circuits by distributing approximation errors in a quantum algorithm are described. A method includes decomposing a quantum algorithm into quantum circuits. The method includes using at least one processor, automatically performing a step-wise decomposition of the quantum algorithm until the quantum algorithm is fully decomposed into the quantum circuits, where the automatically performing the step-wise decomposition results in a set of approximation errors and a set of parameters to instantiate at least a subset of the quantum circuits corresponding to the quantum algorithm, such that an overall approximation error caused by the automatically performing the step-wise decomposition is maintained below a specified threshold approximation error.

Abstract: Data indicative of alignment targets may be received. Each alignment target may be associated with a target location on an object. Locations of the object to be inspected may be identified. An alignment target from the alignment targets may be selected. Each of the locations may be within a determined distance from the selected alignment target. An indication may be provided to align the object relative to an examination tool for inspecting the locations within the determined distance from the selected alignment target.

Abstract: Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.

Abstract: This application discloses a computing system to identify a stage of a logic pipeline described in a circuit design that, when implemented in configurable hardware, spans between partitions in the configurable hardware. The computing system can modify the circuit design to alter a timing for logic operations in the logic pipeline, which reduces slack in at least one stage in the logic pipeline adjacent to the identified stage in the logic pipeline. The computing system can utilize the slack reduced from at least one of the stages adjacent to the identified stage to increase a clock frequency in the configurable hardware or increase a time available for propagation delay associated with the identified stage. The computing system can generate a configuration for the configurable hardware that implements the logic pipeline with the altered timing in the configurable hardware.

Abstract: Methods for reticle enhancement technology (RET) include representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as a function sample array, which is an array of function values. A continuous tone mask (CTM) is provided, where the CTM is used to produce the predicted wafer pattern. Methods for RET also include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.

Abstract: The invention relates to a temperature sensor (5) for measuring a temperature of a battery system (1) for storing electrical energy and also for supplying an electric motor of a motor vehicle with electrical energy. The temperature sensor (5) has a sensor head (6) and connection wires (7) electrically coupled to the sensor head. At least one of the connection wires (7) is at least partially formed as a spring element (8) or forms at least part of a spring element (8), wherein the spring element (8) is formed as a helical spring or as twisted.

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.

Abstract: An embodiment is a system including a first wireless charging pad coupled to a wireless charging system and an energy source, the first wireless charging pad being configured to transmit an energy by a magnetic field. The system further includes a second wireless charging pad coupled to a second system, the second wireless charging pad configured to receive at least a portion of the energy from the first wireless charging system for operating the second system. Further embodiments include a least one of an electronic compass configured to provide alignment data of the first and second wireless charging pads, and an interface configured to receive the alignment data and affect an alignment of the first and second wireless charging pads.

Abstract: A current sense method comprises generating a voltage across a first current mirror of a current sense apparatus, the voltage being proportional to a current flowing through the current sense apparatus when the current is greater than a predetermined current value and applying a minimum drain-to-source voltage limiter to the first current mirror of the current sense apparatus when the current is less than the predetermined current value, wherein, as a result of applying the minimum drain-to-source voltage limiter to the first current mirror, the voltage across the first current mirror is clamped to a predetermined voltage value.

Abstract: Generating reports for critical path evaluation and tuning. A predetermined critical path in a circuit design is detected. The predetermined critical path includes a plurality of interconnects between at least two macros. At least one output or at least one input is detected for each of the at least two macros associated with the predetermined critical path. Additionally, a routing description and a buffer location corresponding to the predetermined critical path are detected and a reduced layout design is built. The reduced layout design includes the predetermined critical path and the at least two macros. Furthermore, a timing report is generated based on the reduced layout design, and a circuit based on the circuit design is manufactured in response to detecting the timing report based on the reduced layout design satisfies a predetermined condition.

Abstract: A battery charging system comprises a battery operated device, a battery charger, and a pair of electrical contacts to electrically connect the battery charger and battery operated device to enable charging the battery, wherein the battery operated device comprises at least a rechargeable battery and short-circuit protection means to prevent discharge of the battery if the electrical contacts become electrically connected, and wherein the battery charger comprises at least monitoring and control circuit to charge the battery.

Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.

Abstract: Devices, methods, computer readable media, and other embodiments are described for design and verification of safety critical electronic systems. Some embodiments integrate functional safety (FS) data with circuit design data for use in electronic design automation (EDA) operations. One embodiment involves a device accessing FS and circuit design data; automatically analyzing register transfer level (RTL) design data using the FS data to perform one or more FS quality checks; and placing and routing the circuit design using the RTL design data and the set of FS data to perform FS-aware placement and routing. In some embodiments, failure modes and associated safety mechanisms to improve safety metrics associated with failure modes are automatically added to the circuit design during EDA operations. In other embodiments, additional FS-aware operations are performed. In some embodiments, the FS data is structured as a single Unified Safety Format (USF) file.

Abstract: Routing a circuit design for implementation in an integrated circuit having a programmable network on chip can include determining Quality of Service (QOS) parameters for data flows of a circuit design, wherein the data flows involve transfers of data between masters and slaves through the programmable network on chip and generating, using a processor, an expression having a plurality of variables representing the data flows, routing constraints, and the QOS parameters. A routing solution can be determined using the processor for the data flows of the circuit design by initiating execution of a SAT solver using the expression.

Abstract: An embodiment of a thermal estimation device including a temperature model generator, a temperature gradient calculator, and a thermal sensing analyzer is disclosed. The temperature model generator generates a temperature model based on an initial power consumption, an initial area and an initial coordination of a circuit module. The temperature gradient calculator substitutes at least one of a testing area, a testing power or a testing coordinate of the circuit module into the temperature model for correspondingly estimating an temperature estimation function. The thermal sensing analyzer differentiates the temperature estimation function. When an absolute value of a differential result of the temperature estimation function resulted from a constant is closest to zero or is zero, outputting the constant as an optimized parameter.

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, a first stimulus parameter of the at least two stimulus parameters comprising an input to an input pin of the electronic circuit defined by the electronic design file, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least two stimulus parameter stored in at least one specification database and at least one measurement parameter st

Abstract: A power supply is disclosed for an industrial control system or any system including a distributed power supply network. In embodiments, the power supply comprises: a battery module including a battery cell and a battery monitor configured to monitor the battery cell; and a self-hosted server operatively coupled with the battery module, the self-hosted server being configured to receive diagnostic information from the battery monitor and provide network access to the diagnostic information. In implementations, the diagnostics stored by the self-hosted server can be broadcast to or remotely accessed by enterprise control/monitoring systems, application control/monitoring systems, or other remote systems via a secured network (e.g., secured access cloud computing environment).

Abstract: A logic model of a nonvolatile memory device is commonly used in high order synthesis and a logic simulation. Further, the logic model of the nonvolatile memory device divides a one-time rewriting request area of the nonvolatile memory device into a plurality of areas, and rewrites each of the divided areas in a time division manner.

Abstract: Data is received that characterizes an integrated circuit and which includes a plurality of Standard Test Interface Language (STIL) codes and at least one file defining physical and/or logical parameters of the integrated circuit. Thereafter, using the received data, a power integrity analysis of the integrated circuit is performed to estimate power induced noise in a double glitch capture mode. Data is then provided that characterizes the performed double glitch capture mode power integrity analysis of the integrated circuit. Related apparatus, systems, techniques and articles are also described.

Abstract: A computer implemented method of passive verification of an electronic design, comprising receiving an electronic design file of said electronic design comprised at least in part of a mixed signal or analog system including a plurality of subsystems. At least one analog subsystem of the plurality of subsystems has at least two design representations within the electronic design file that are intended to be equivalent for the at least one analog subsystem being simulated. First and second input subsystem data is collected for a first and second subsystem design representation of the at least two design representations from an analog stimulus to at least one input of the first and second subsystem design representation which is analog.