Abstract: A SAR converter having enhanced performance by virtue of effectively pre-loading the SAR's most significant bits with a value that makes the associated DAC output almost equal to the signal to be converted. A normal SAR conversion is then completed with the SAR bits that have not been pre-loaded. The value used to pre-load the most significant bits of the SAR is preferably obtained from a low-resolution, high-speed converter, such as a flash. The range of DAC bits used in the normal SAR part of the conversion may be increased such that errors up to a certain magnitude in the high-speed converter can be corrected. A method for performing an enhanced SAR conversion is also described.

Abstract: The invention relates to an integrated HF circuit with attenuators, exhibiting an input, an output, and a number of field effect transistors as switching elements with a number of positive supply voltages, wherein the attenuators control, according to an attenuation state, which can be switched between two states, the amplitude of a reference signal, applied to the input, and produces an actual signal at the output. According to the invention, the attenuators exhibit a number of inductors and/or capacitors for phase compensation, and the field effect transistors may be driven without power.

Abstract: An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

Abstract: This present invention is directed to a stage circuit for a pipelined analog-to-digital converter. The stage circuit includes an amplifier, a comparator, a first compensator and a second compensator, and three modes are developed for the stage circuit in signal processing: a sampling mode, a first amplifying mode and a second amplifying mode. In the sampling mode, the amplifier is inputted with an analog input signal; the comparator compares the analog input signal with a reference signal, and then generates a first digital output code. In the first amplifying mode, the first compensator selectively adds a first compensation value to the analog input signal according to the first digital output code, and then generates a first input signal; the amplifier amplifies the first input signal and then generates a first output signal; the comparator compares the first output signal with the reference signal and then generates a second digital output signal.

Abstract: The present invention is to provide a logic circuit which assures short-circuit current reduction by using a gate which uniquely fixes the level of each node and also reduces leakage current so that the power is turned on and off quickly. Logic gates of the subject logic circuit are divided into first-type logic gate and second-type logic gates. The first-type logic gate outputs high potential under the specific status and the second-type logic gate outputs low potential under the specific status. Under the state that the high potential is supplied to the first-type logic gates and the low potential is supplied to the second-type logic gates, the power switch MOS is turned on. Further, in case of the adder, the specific status is equal to selecting a constant as an input of the adder. For general logic circuit, specific flip-flops are introduced to implement this specific status.

Abstract: Estimating a compression gain obtainable in compressing a given audio signal, comprising extracting a signal power in a selected frequency band of the given audio signal, and obtaining an estimation of the compression gain by correlation with the extracted signal power.

Abstract: A method for compressing an input sequence of data portions to produce an output codestream and for partially decompressing the output codestream to obtain a selected segment of the input sequence is disclosed. The output codestream includes a sequence of non-matchable sequences and codewords. The codewords include a first codeword and subsequent codewords. Each of the codewords includes at least a length of a subsequent non-matchable sequence preceding a matchable first sequence. Each of the subsequent codewords further includes a first offset for indicating a start of the matchable first sequence in the preceding non-matchable sequence, a length of the matchable first sequence and a second offset for indicating a location of a preceding codeword in the output codestream. A program storage device and a compressing/decompressing system for providing the above method are also disclosed.

Abstract: A laminated low-profile dual filter module for telecommunications devices and method provides both Groupe Spécial Mobile (GSM) and Digital Cellular System (DCS) transmit filters in a small package. The filter module comprises multiple layers of ceramic substrate with metal circuit patterns sandwiched between. Two separate filters are implemented within the layers, with a first filter comprising a first set of layers and the second filter adjoining within a second set of layers. Resonators for each filter are positioned at the opposite sides of the module, in order to avoid coupling between the resonators and ground layers are interspersed for isolation. Capacitors are implemented by a first plate defined by an area on one metal layer with the adjacent layers providing ground planes that form the second plate.

Abstract: Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes inductive and resistive loads to equalize the gain over the frequency of interest to reduce data-deterministic jitter.

Abstract: A termination resistor circuit includes a first and second passive resistive elements coupled in series between a common mode voltage and a signal node, and a plurality of active resistive elements coupled in parallel with the first passive resistive element. The active resistive elements may be selectively enabled by corresponding control signals to provide various numbers of parallel resistances across the first passive resistive element, thereby tuning the termination resistor circuit to a desired resistance value.

Abstract: A VCO (110) can be configured to convert an analog input signal (105) to a digital output signal (125). In accordance with the inventive arrangements, the VCO can convert the analog input signal to at least one intermediate signal (130) having a frequency dependent on the analog input signal. A frequency detector (115) can be configured to determine a frequency of at least one intermediate signal. Subsequently, a mapping circuit (120) can be configured to map the determined frequency of the at least one intermediate signal to an output value representing the digital output signal (125).

Abstract: An A/D converter includes first to Nth stages of A/D conversion units, which are connected in series, each A/D conversion unit converting an analog input signal into a digital output signal. Each of the A/D conversion units includes a) a sample-and-hold circuit, which holds an analog input signal; b) a selector which selects one from a plurality of reference voltage signals in accordance with a digital output signal outputted from the one stage preceding A/D conversion unit; and c) a comparator which compares an output signal supplied from the sample-and-hold circuit with the reference voltage signal selected by the selector.

Abstract: A multi-channel circuit (1) comprising three channels (CH1 to CH3), each of which is provided with a current steering DAC (5) in which crosstalk between the respective DACs (5) is minimized. Each DAC (5) comprises binary scaled current source devices (Qs1 to Qsn) and current steering switches (Qt1 and Qf1 to Qtn to Qfn) for steering currents from the current source devices (Qs1 to Qsn) to summing nodes (11,12) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Qc1 to Qcn) are provided between the respective current source devices Qs1 to Qsn and the corresponding current steering switches (Qt1 and Qf1 to Qtn and Qfn) for preventing capacitive feedthrough of voltage swings on the current steering switches (Qt1 and Qf1 to Qtn and Qfn) for minimizing crosstalk between the DACs (5).

Abstract: An end-surface reflection type surface acoustic wave filter is capable of increasing an attenuation amount outside a pass band while insertion loss characteristics are not seriously deteriorated. The filter is a longitudinally coupled resonator type surface acoustic wave filter using an SH type surface acoustic wave, which has first and second grooves formed in a piezoelectric substrate at the top surface thereof so as to be substantially parallel to each other and spaced from each other by a predetermined distance. In addition, IDTs which are provided between the grooves for defining the longitudinally coupled resonator type surface acoustic wave filter, reflection end-surfaces disposed on side surfaces of the first and the second grooves at the IDT sides, and one of a resin-coating layer and a protective layer made of SiO2, are provided on the top surface of the piezoelectric substrate.

Abstract: An analog FIR-filter comprising an asynchronous &Sgr;&Dgr; modulator (AM) generating amplitude-discrete time-continuous pulses coupled to a sequence of delay cells (C1 . . . Cn) for delaying the amplitude-discrete time-continuous pulses. One or more output devices (O1, On, S1, Sn, I1, In) for low pass filtering of the delayed amplitude-discrete time-continuous pulses.

Abstract: A circuit substrate includes resistive films are disposed on the surfaces of lands included in a circuit pattern and these resistive films are used as resistances connected in series to a capacitor. Therefore, the resistances are connected in series without increasing the inductance in the capacitor, and accordingly, a circuit having a small impedance variation with respect to frequency can be obtained. Therefore, it is possible to obtain a power supply circuit and so forth having stable operation and fast response.

Abstract: An apparatus for reproducing digital information coded in a coding system, the coded digital information and a decoding program describing a decoding algorithm to decode the digital information recorded in an information recording medium, includes: a reading unit configured to read out the coded digital information and the decoding program recorded in the information recording medium; a program memory configured to store the decoding program read out from the reading unit; a signal processing unit configured to decode the digital information read out from the reading unit by the decoding algorithm of the decoding program stored in the program memory; and a conversion unit configured to convert the digital information decoded in the digital signal processing unit into a predetermined format, and to output the converted digital information.

Abstract: Data modulating/demodulating method and system and apparatus using the same. The modulation method with smaller modulation table, compared to the conventional modulation table, is used to modulate the source data to the channel bits to be recorded to an external storage apparatus, such as optical disc. The demodulation method with smaller demodulation table, compared to the conventional demodulation table, is used to demodulate the bit data stream recorded on a storage apparatus, such as optical disc, to the original source data.

Abstract: According to one form of the invention, an apparatus includes first timing circuitry, at least one stage of logic circuitry and second timing circuitry. The first timing circuitry has a first data input and a latch with a latch data input coupled to the first data input and a latch data output coupled to an input of the least one stage of logic circuitry. The second timing circuitry has a latch and an edge detector with respective latch and edge detector data inputs coupled to a data output of the at least one stage of logic circuitry. The edge detector has an output coupled to a control input of the second timing circuitry latch for triggering capture of an output data signal on the data output of the at least one stage of logic circuitry responsive to detecting a signal transition.

Abstract: A parallel/serial conversion circuit is provided, which comprises a parallel/serial conversion section for converting first parallel data to first serial data and converting second parallel data to second serial data, and a shift clock signal generation section for generating a shift clock signal. The parallel/serial conversion section converts the first parallel data to the first serial data by shifting the first parallel data in response to the shift clock signal. The parallel/serial conversion section converts the second parallel data to the second serial data by shifting the second parallel data in response to the shift clock signal. A combination of the first serial data and the second serial data indicates bit separation, a logic value ‘0’, or a logic value ‘1’. The shift clock signal generation section generates the shift clock signal by combining the first serial data and the second serial data.