Abstract: A semiconductor integrated circuit device includes a plurality of flip-flops, each of which has an external input terminal and external output terminal, the flip-flops being cascade-connected by having data output terminals respectively connected to data input terminals of the next-stage flip-flops. A reset signal is input via the external input terminal of the first-stage flip-flop and is sequentially transferred from the external output terminal thereof to the next-stage flip-flops. The reset signal is transferred via a transmission path different from the original data transmission path to reset all of the flip-flops.

Abstract: In a status scheme signal processing circuit which obtains a desired output signal on the basis of an OR signal between a pulse output from a one-shot pulse circuit at an edge of an input signal and a status signal, since the input signal and the status signal are not synchronized with each other, the output timing of the output signal changes depending on the timing of the input signal. Therefore, in the present invention, a mask signal generator which outputs a mask signal having a predetermined bandwidth T1 in response to a signal leading edge and a signal trailing edge of the input signal, and said desired output signal is masked (disabled) with the mask signal, so that an output signal is always obtained a predetermined period (T1) after the input timing of the input signal.

Abstract: A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one.

Abstract: Device converts an analogue signal representing charges resulting from the photo-detection of electromagnetic radiation into a digital signal. Device includes (a) a number of photo-detectors connected in rows and columns through of buses, the photo-detectors in one column sharing the same column bus, itself connected to an output stage by through a row bus, and between each photo-detector and the column bus, (b) an integrator, to integrate the charges arriving from the photo-detector, (c) means for resetting the integrator, and (d) a comparator to compare the voltage Vp from the integrator with an internally predefined threshold voltage Vs, characterized in that it also includes a processing device, a clock, the clock controlling the processing device and the processing device receiving a binary value present at the output of the comparator at each signal from the clock.

Abstract: A coder and/or decoder system and method are provided including a variable modulus. As an option, the modulus may reflect a steepness of a probability distribution curve associated with a compression algorithm (i.e. a negative exponential of the probability distribution). Moreover, the modulus may depend on a context of a previous set of data, while avoiding increasing as a function of a run length (i.e. a plurality of identical bits in a sequence).

Abstract: An apparatus for use as both an off chip driver (OCD) and an on die termination (ODT) circuits. A preferred embodiment comprises a control circuit (for example, control circuit 305) coupled to a dual function OCD/ODT circuit (for example, OCD/ODT circuit 330) with an enable line coupled to the control circuit. The control circuit may be used to selectively choose OCD and ODT functionality based on a value on the enable line. With the control circuit choosing OCD, the dual function OCD/ODT circuit functions as an OCD circuit, placing signals provided through the control circuit onto a transmission line. With the control circuit choosing ODT, the dual function OCD/ODT circuit becomes terminating resistors for incoming signals on a transmission line. The use of a single circuit for both OCD and ODT functions can save both integrated circuit real-estate and implementation costs due to a reduction in use of circuit elements.

Abstract: An integer coding method supporting diverse frame sizes and a coder-decoder (CODEC) implementing the method are provided. Maximum sample values are detected from a plurality of frames having different numbers of samples. The detected maximum sample values are normalized on the basis of a maximum sample value of the largest frame. A maximum sample value is detected from the normalized sample values. Multiples are determined according to the size of each frame on the basis of the detected maximum sample value and a sample value of each frame is multiplied by the multiples to generate an integer code.

Abstract: Methods and devices for converting an analog input signal into a digital output signal by means of an analog-to-digital converter are provided. The analog input signal is multiplied by a first adjustable scaling factor to form an analog intermediate signal. The analog intermediate signal is converted into a digital representation. The digital representation is multiplied by a second adjustable scaling factor to form a sample signal, and a third adjustable scaling factor to form the digital output signal. The level of the sample signal is determined and compared to first and second threshold values, with the first threshold value being greater than the second threshold value. The first adjustable scaling factor is increased and the second and third adjustable scaling factors are decreased if the sample signal level is higher than the first threshold value.

Abstract: A fractional-N frequency synthesizer includes a voltage-controlled oscillator, a dual-modulus divider which divides an output frequency of the voltage-controlled oscillator according to a fractional control input, and a phase comparator which compares a phase of an output of the dual-modulus divider with a phase of a reference frequency, where an output of the phase comparator controls an input of the voltage-controlled oscillator. The synthesizer further includes a sigma-delta modulator which has a single-bit output, and a bit converter which converts the single-bit output of the sigma-delta modulator to the fractional control input applied to the dual-modulus divider.

Abstract: Variable length decoding of DCT coefficients in MPEG video data is performed using a standard processor (400) and a small look-up table (LUT 530). The processor performs (520) an integer to floating point conversion on a portion the received bitstream (BS). By this step, lengthy codewords with many leading zeros, which are common in the codebook, are represented in a compressed form by the exponent and mantissa fields (EXP, MAN) of the floating point result (FP). The relevant bits are extracted and used as an index (IX) to address the LUT. This avoids cumbersome bit-oriented logic, while also avoiding a very large LUT that would otherwise be required to represent the same codebook. The entire LUT may thus reside in cache memory (410). In a VLIW processor implementation, decoding of one token is pipelined with the inverse scan and inverse quantisation step of the preceding token(s).

Abstract: Methods and devices for code independent switching in signal processing circuit such as a digital-to-analog converter (DAC) are described, which provide code independent switching activity. A steering cell receives a digital data input signal that is defined at data intervals, and produces multiple representative analog output signals. For each data interval, each analog output signal depends only on the present state of the digital data input signal, independently of any previous state of the digital data input signal. In addition, the signal processing circuit apart from the analog output signals is substantially free of data dependent disturbances.

Abstract: A method and circuit that supplies valid logic values at an end of a transmission line for sampling on high speed interfaces, such as HSTL and SSTL, during reset. The circuit may include operational amplifiers and resistors.

Abstract: A mixed-voltage I/O buffer circuit that prevents leakages through a driver stage PMOS transistor is provided. The buffer circuit has a first part that prevents leakage through a parasitic diode of the transistor and a second part that prevents leakage through the transistor when the transistor is turned on by a signal on a bonding pad having a voltage level higher than a power supply voltage of the buffer circuit. The buffer circuit provides biases approximately equal to the high voltage signal to a gate and a substrate terminal of the PMOS transistor when the bonding pad has the high voltage signal thereon, and provides a bias approximately equal to the power supply voltage of the buffer circuit to the gate and substrate of the PMOS transistor when the bonding pad has a low voltage signal thereon.

Abstract: An analog to digital converter includes a first charging circuit that samples an input voltage during a charging phase. A first opamp has an input that communicates with the first charging circuit during an integrating phase. A first current source selectively generates a first bias current for the first opamp during the charging phase and a second bias current that is not equal to the first bias current during the integrating phase. The first bias current is less than the second bias current. The first current source can be a variable current source that selectively provides the first and second bias currents during the charging and integrating phases, respectively. Alternately, the first current source can include two current sources. Only one of the two current sources is connected to the first opamp during the integrating phase.

Abstract: A signal generator controls power output on the basis of the output from a &Dgr;-&Sgr; modulator or oscillator. That output may be generated in real time by the modulator or oscillator and fed to a switch control logic unit which controls a power switching stage to output switchably switched power from a power supply to an output, preferably via a filter. Alternatively the output of a &Dgr;-&Sgr; oscillator or modulator may be stored in a switchable memory to be retrieved when needed. A further alternative is to control the power switching stage by a processor with a program which reproduces the control effect of the &Dgr;-&Sgr; oscillator/modulator. Feedback from the output may be used to control the &Dgr;-&Sgr; modulator/oscillator and/or the power supply.

Abstract: A digitizer module comprises an AD converter for sampling a pair of analog signals at a predetermined time interval and converting into a first and second digital signals respectively, a second signal frequency component calculating unit for calculating a second signal frequency component representing a component of each frequency of the second digital signal on the basis of the second digital signal, a skew frequency component calculating unit for calculating a skew frequency component representing a phase error of each frequency of the second digital signal corresponding to the first digital signal on the basis of a skew of a timing with which the pair of analog signals are sampled by the AD converter and a second signal frequency component correcting unit for correcting the second signal frequency component on the basis of the skew frequency component.

Abstract: The present invention proposes an output signal circuit capable of automatically detecting polarity, whose input/output signal terminal of the output signal circuit has both input and output functions. When a system undergoes a power on reset or a hardware reset, the output signal circuit can be shut off, and the input state of the input/output signal terminal is used to set the polarity of output signal. After reset, the pin is restored to its normal output. When an IC has the output signal capable of automatically detecting polarity, the flexibility in design of application circuits can be enhanced. Limitation of usage of IC due to fixed polarity of output signal can thus be avoided.

Abstract: A method for designing a single loop Sigma Delta Modulator, and a single loop Sigma Delta Modulator. A microphone comprising the above Sigma Delta Modulator (SDM) and a cellular phone or hearing aid incorporating the microphone. A design algorithm for an SDM is described said method resulting in a SDM with a maximum SNR for a given NTF order and the method assures stability while still keeping the distortion in the output signal at a minimum for signals exceeding MSA. The method further takes the presence of non idealities in i.e. components into consideration and makes the SDM less sensitive to these non idealities. Furthermore the method tailors the coefficients and the design of the NTF to fit a low power low voltage integrated circuit implementation.

Abstract: An integrated circuit (1) comprises a microprocessor (2), an ADC (3) and a serial interface (4) for communicating the integrated circuit with an external device. An analogue input port (5) is provided for inputting analogue signals to the ADC (3). A switch circuit (8) is provided for selectively and alternately configuring the integrated circuit (1) to operate in a first mode and in a second mode. In the first mode the serial interface (4) communicates with the microprocessor (2) through the switch circuit (8), and in the second mode the serial interface (4) communicates with the ADC (3) through the switch circuit (8). In the second mode conversion results are transferred from the ADC (3) through the switch circuit (8) to the serial interface (4) independently of the microprocessor (2) for transmission therefrom to an external device. In the first mode the ADC (3) is operable under the control of the microprocessor (2).

Abstract: A highly compact band pass filter that has excellent mechanical strength is disclosed. A band pass filter according to the present invention employs a dielectric block of substantially rectangular prismatic shape constituted of a first portion lying between a first cross-section of the dielectric block and a second cross-section of the dielectric block substantially parallel to the first cross-section and second and third portions divided by the first portion and metal plates formed on surfaces of the dielectric block. The first portion of the dielectric block and the metal plates formed thereon are enabled to act as an evanescent waveguide. The second portion of the dielectric block and the metal plates formed thereon are enabled to act as a first resonator. The third portion of the dielectric block and the metal plates formed thereon are enabled to act as a second resonator. The metal plates include at least one exciting electrode formed on a first surface of the dielectric block which has the widest area.