Abstract: The invention relates to a novel memory cell structure and process to fabricate chalcogenide phase change memory. More particularly, it produces a small cross-sectional area of a chalcogenide-electrode contact part of the phase change memory, which affects the current/power requirement of the chalcogenide memory. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: A thin film transistor array substrate includes a gate line formed on a substrate, a data line formed on the substrate intersecting with the gate line to define a pixel region, a thin film transistor formed at the intersection of the gate line and the data line, the thin film transistor including gate electrode formed on the substrate, a gate insulating layer formed on the gate electrode and the substrate, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer on the semiconductor layer, and a source electrode and a drain electrode on the ohmic contact layer, and a transparent electrode material within the pixel region and connected to the drain electrode of the thin film transistor, wherein the gate insulating layer includes a gate insulating pattern underlying the data line and the transparent electrode material, and covering the gate line.

Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.

Abstract: Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.

Abstract: A complementary bipolar transistor is fabricated using an available portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.

Abstract: The present invention provides a wavelength-convertible LED which has first and second surfaces, including first and second conductivity-type cladding layers and an active layer formed between the first and second conductivity-type cladding layers to emit a specific wavelength light. The invention also includes at least a piezoelectric layer on at least one of the first and second surfaces of the semiconductor LED with its thickness variable according to the applied voltage, and a rigid frame made of substantially non-resilient rigid material surrounding the semiconductor LED and the at least one piezoelectric layer such that the increase of the thickness of the piezoelectric layer is applied to the semiconductor LED as pressure. The invention further includes a plurality of terminals on the rigid frame, connected to the first and second conductivity-type cladding layers, and the piezoelectric layer.

Abstract: A light receiving or light emitting modular sheet having a plurality of spherical elements arranged in matrix. It is constituted only of acceptable spherical elements and photoelectric conversion efficiency thereof is enhanced. The light receiving modular sheet (1) comprises a plurality of spherical solar cell elements (2) arranged in matrix, a meshed member (3), and a sheet member (4). Each solar cell element (2) comprises a spherical pn junction (13), and positive and negative electrodes (14, 15) formed oppositely while sandwiching the center of the solar cell element (2) and being connected with respective electrodes of the pn junction (13).

Abstract: An improvement in electrode reliability is realized by preventing over-etching on a peripheral lower portion of an electrode while maintaining the flow of steps of roughening a surface after forming the electrode on a semiconductor substrate. After a P-side electrode 4 is formed on a main surface 3a of a semiconductor substrate 3, a surface of the P-side electrode 4 is selectively covered with a protective film 12, after the semiconductor substrate 3 is cut into chips, the surface is roughened from above the protective film 12, the main surface 3a around the P-side electrode 4 and a side surface are roughened with a non-chemical treatment region 10 which is a non-roughened surface region being left in a peripheral portion of the P-side electrode 4 covered with the protective film 12, and thereafter the protective film 12 is removed.

Abstract: The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring method thereof. Since a thin film transistor substrate of the present invention comprises three-dimensionally cross-linked self-assembled monolayers between the Si surface and the metal wiring, it has good adhesion ability and anti-diffusion ability.

Abstract: A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation. For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase. Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields. These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels.

Abstract: A semiconductor device has an, improved mounting reliability and has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads positioned outside the semiconductor chip are connected with electrodes formed on the semiconductor chip through wires.

Abstract: Organic semiconductor-based devices such as thin film transistors, organic light emitting devices and solar cells have potential in low cost electronic and optoelectronic applications. The performance of these organic semiconductor-based devices is often limited by the large resistance between the organic semiconductors and counter electrodes. This invention provides device structures and methods to reduce the unwanted resistance.

Abstract: A QWIP structure is disclosed that includes a graded emitter barrier and can further be configured with a blocked superlattice miniband. The graded emitter barrier effectively operates to launch dark electrons into the active quantum well region, thereby improving responsivity. A graded collector barrier may also be included for reverse bias applications. The configuration operates to eliminate or otherwise reduce image artifacts or persistence associated with dielectric relaxation effect in low-background applications.

Abstract: A method of manufacturing a microelectronic device comprising forming a patterned feature over a substrate and employing a fluorine-containing plasma source to deposit a conformal polymer layer over the patterned feature and the substrate. The polymer layer is etched to expose the patterned feature and a portion of the substrate, thereby forming polymer spacers on opposing sides of the patterned feature.

Abstract: A memory element wherein a spin conduction layer having a sufficient spin coherence length and a uniform spin field can be obtained, and thereby practical use is attained and a memory device are provided. A spin conduction layer (paramagnetic layer) (24) is a fullerene thin film being from 0.5 nm to 5 ?m thick, for example. The fullerene has a hollow sized, for example, from 0.1 nm to 50 nm. A paramagnetic material is included in this hollow. A fermi vector of the fullerene thin film well laps over small number of spin band or plenty of spin band of a ferromagnetic fixed layer (23) and a ferromagnetic free layer (25). Further, spin orientations of the included paramagnetic material are random. Further, electron spin in the fullerene is in a quantized state in a pseudo zero dimensional space. Thereby, a spin coherence length becomes long in the fullerene thin film, and scatteration of spin-polarized conduction electrons goes away.

Abstract: Two or more of striped structures are formed in one chip, and a relaxation oscillation frequency of the first striped structure is greater than a relaxation oscillation frequency of the second striped structure. An RIN value at low output is improved by the first striped structure having a higher relaxation oscillation frequency, and a single transverse mode and reliability at high output are obtained by the second striped structure having a lower relaxation oscillation frequency.

Abstract: Provided are a nitride-based light emitting device using a p-type conductive transparent thin film electrode layer and a method of manufacturing the same. The nitride-based light emitting device includes a substrate, and an n-cladding layer, an active layer, a p-cladding layer and an ohmic contact layer sequentially formed on the substrate. The ohmic contact layer is made from a p-type conductive transparent oxide thin film. The nitride-based light emitting device and method of manufacturing the same provide excellent I-V characteristics by improving characteristics of an ohmic contact to a p-cladding layer while enhancing light emission efficiency of the device due to high light transmittance exhibited by a transparent electrode.

Abstract: A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer is disposed between the source or drain region of the PMOS transistor and an overlying surface tension-inducing layer. The surface tension-inducing layer may comprise a nitride material or carbon-containing material, and the surface tension-reducing layer may comprise an oxide material. Degradation of hole mobility in the PMOS transistor is prevented by the use of the surface tension-reducing layer of the bilayer etch stop.

Abstract: An electro luminescence display device is adapted for preventing the deterioration of an organic light-emitting layer by ultraviolet rays during a sealing process, and a transparent substrate; an organic light-emitting layer formed on the transparent substrate; a packaging plate bonded with the transparent substrate by a sealant to cover the organic light-emitting layer; and a light-intercepting member to prevent ultraviolet rays illuminated onto the sealant during bonding the transparent substrate with the packaging plate from being reflected by the packaging plate onto the organic light-emitting layer.

Abstract: The invention relates to a light source comprising a light-emitting element, which emits light in a first spectral region, and comprising a luminophore, which comes from the group of alkaline-earth orthosilicates and which absorbs a portion of the light emitted by the light source and emits light in another spectral region. According to the invention, the luminophore is an alkaline-earth orthosilicate, which is activated with bivalent europium and whose composition consists of: (2-x-y)SrOx(Ba, Ca)O (1-a-b-c-d)SiO2 aP2O5 bAl2O3 cB2O3 dGeO2: y Eu2+ and/or (2-x-y)BaO x((Sr, Ca)O (1-a-b-c-d)SiO2 aP2O5 bAl2O3 cB2O3 dGeO2: y Eu2+. The desired color (color temperature) can be easily adjusted by using a luminophore of the aforementioned type.