Patents Examined by Sara Crane
  • Patent number: 7180092
    Abstract: There is provided a semiconductor device including a picture display function and a picture capturing function on the same substrate. The semiconductor device includes a pixel matrix, an image sensor, and a peripheral circuit for driving those, which are provided on the same substrate. Moreover, in the semiconductor device, the structure/manufacturing process of the image sensor is made coincident with the structure/manufacturing process of the pixel matrix and the peripheral driver circuit, so that the semiconductor device can be manufactured at low cost.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: February 20, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 7179670
    Abstract: A light emitting diode (10) has a backside and a front-side with at least one n-type electrode (14) and at least one p-type electrode (12) disposed thereon defining a minimum electrodes separation (delectrodes). A bonding pad layer (50) includes at least one n-type bonding pad (64) and at least one p-type bonding pad (62) defining a minimum bonding pads separation (dpads) that is larger than the minimum electrodes separation (delectrodes). At least one fanning layer (30) interposed between the front-side of the light emitting diode (10) and the bonding pad layer (50) includes a plurality of electrically conductive paths passing through vias (34, 54) of a dielectric layer (32, 52) to provide electrical communication between the at least one n-type electrode (14) and the at least one n-type bonding pad (64) and between the at least one p-type electrode (12) and the at least one p-type bonding pad (62).
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: February 20, 2007
    Assignee: GELcore, LLC
    Inventors: Bryan S. Shelton, Sebastien Libon, Hari S. Venugopalan, Ivan Eliashevich, Stanton E. Weaver, Jr., Chen-Lun Hsing Chen, Thomas F. Soules, Steven LeBoeuf, Stephen Arthur
  • Patent number: 7180172
    Abstract: A dielectric material for use in a circuit material comprises a liquid crystalline polymer and a polyhedral oligomeric silsesquioxane (POSS) filler. Such dielectric materials may provide a variety of advantageous properties, especially in high frequency circuits.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: February 20, 2007
    Assignee: World Properties, Inc.
    Inventors: Murali Sethumadhavan, Scott D. Kennedy, Carlos L. Barton
  • Patent number: 7176499
    Abstract: When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III-V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III-V compound semiconductor substrate composed of a first region in form of a crystal having a first average dislocation density and a plurality of second regions having a second average dislocation density higher than the first average dislocation density and periodically aligned in the first region, device regions are defined on the nitride III-V compound semiconductor substrate such that the device regions do not substantially include second regions, emission regions or active regions of devices finally obtained do not include second regions.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: February 13, 2007
    Assignees: Sony Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Tsunenori Asatsuma, Shigetaka Tomiya, Koshi Tamamura, Tsuyoshi Tojo, Osamu Goto, Kensaku Motoki
  • Patent number: 7173288
    Abstract: A nitride semiconductor light emitting device including a light emitting diode and a diode formed on a single substrate, in which the light emitting diode and the diode use a common electrode. According to the present invention, an active layer and a p-type nitride semiconductor layer are each divided into a first region and a second region by an insulative isolation layer, and an ohmic contact layer is formed on the p-type nitride semiconductor layer contained in the first region. A p-type electrode is formed on the ohmic contact layer and is extended to the p-type nitride semiconductor layer contained in the second region. An n-type electrode is formed on the p-type nitride semiconductor layer contained in the second region, passes through the p-type nitride semiconductor layer and the active layer contained in the second region, and is connected to the first n-type nitride semiconductor layer.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: February 6, 2007
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyu Han Lee, Hyun Kyung Kim, Je Won Kim, Dong Joon Kim
  • Patent number: 7173294
    Abstract: The CCD image sensor addresses the problem of noise, due to background charge generated by Compton scattering of gamma rays. In applications, in which an imager must operate in a high-radiation environment, such background noise reduces the video signal/noise. This imager reduces the amount of charge collected from Compton events, while giving up very little sensitivity to photons in the visible/near IR.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 6, 2007
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Barry E. Burke, Robert K. Reich
  • Patent number: 7173284
    Abstract: A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer, and first gate areas are formed on inner walls of the trenches. Second gate areas are formed in isolation from the first gate areas. A source area is formed on channel areas, which are located between the first and second gate areas in the drift layer. A method of manufacturing the device ensures uniform channel layer quality, which allows the device to have a normally-off characteristic, small size, and a low likelihood of defects.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: February 6, 2007
    Assignee: Denso Corporation
    Inventors: Rajesh Kumar, Tsuyoshi Yamamoto, Hiroki Nakamura
  • Patent number: 7170097
    Abstract: An electronic device includes a conductive n-type substrate, a Group III nitride active region, an n-type Group III-nitride layer in vertical relationship to the substrate and the active layer, at least one p-type layer, and means for providing a non-rectifying conductive path between the p-type layer and the n-type layer or the substrate. The non-rectifying conduction means may include a degenerate junction structure or a patterned metal layer.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: January 30, 2007
    Assignee: Cree, Inc.
    Inventors: John Adam Edmond, Kathleen Marie Doverspike, Michael John Bergmann, Hua-Shuang Kong
  • Patent number: 7170143
    Abstract: On the front side of an n-type semiconductor substrate 5, p-type regions 7 are two-dimensionally arranged in an array. A high-concentration n-type region 9 and a p-type region 11 are disposed between the p-type regions 7 adjacent each other. The high-concentration n-type region 9 is formed by diffusing an n-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 as seen from the front side. The p-type region 11 is formed by diffusing a p-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 and high-concentration n-type region 9 as seen from the front side. Formed on the front side of the n-type semiconductor substrate 5 are an electrode 15 electrically connected to the p-type region 7 and an electrode 19 electrically connected to the high-concentration n-type region 9 and the p-type region 11.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: January 30, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Tatsumi Yamanaka
  • Patent number: 7170113
    Abstract: An aspect of a semiconductor device includes: a collector layer of first conductive type formed on a semiconductor substrate; a graft base layer of second conductive type formed in a surface region of the collector layer; a first base leading-out region of second conductive type formed on the graft base layer; a second base leading-out region of second conductive type formed on an upper surface and a side surface of the first base leading-out region; a base layer of second conductive type formed on the collector layer; an emitter layer of first conductive type formed in a surface region of the base layer; and an emitter leading-out region formed on the emitter layer.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: January 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Noboru Noda
  • Patent number: 7169684
    Abstract: An LC device having a substrate, a support layer having upper and lower sides formed on the substrate, inductors formed on either the upper or lower side of the support layer, and capacitors formed in the opposite side of the support layer. The support layer may be formed of a low-k dielectric material, and a connection portion may be provided to connect the inductors and capacitors in the support layer. The inductors and capacitors are disposed in a stacked structure on the upper and lower sides of the low-k dielectric support layer on the substrate, so that space efficiency may be maximized on the substrate. The low-k dielectric support layer provides support between the inductors and capacitors so that substrate loss is minimized and a Q factor of the inductors is enhanced.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: January 30, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-chul Lee, In-sang Song, Young-tack Hong, Sung-hye Jeong, Jeong-yoo Hong
  • Patent number: 7169631
    Abstract: A light-emitting device and optical communication system based on the light-emitting device is disclosed. The light-emitting device is formed in a float-zone substrate. The light-emitting device includes on the substrate lower surface a reflective layer and on the upper surface spaced apart doped regions. The portion of the upper surface between the doped regions is textured and optionally covered with an antireflection coating to enhance light emission. The light-emitting device can operate as a laser or as a light-emitting diode, depending on the reflectivities of the antireflection coating and the reflective layer.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: January 30, 2007
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Tanay Karnik, Jianping Xu, Shekhar Y. Borkar
  • Patent number: 7166892
    Abstract: The on resistance per unit area of integration of a DMOS structure is reduced beyond the technological limits of a mask that is defined based upon the continuity of a heavily doped superficial silicon region along the axis of the elongated source island openings through the polysilicon gate layer in the width direction of the integrated structure. The mask no longer needs to be defined with a width (in the pitch direction) sufficiently large to account for the overlay of two distinct and relatively critical masks. These two masks are the source implant mask and the body contacting plug diffusion implant contact opening mask.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: January 23, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventor: Daniele Alfredo Brambilla
  • Patent number: 7166864
    Abstract: A liquid crystal display (LCD) panel is fabricated with a reduced number of mask processes and includes a thin film transistor (TFT) array substrate and a color filter array substrate. The TFT array substrate includes gate and data lines insulatively crossing each other to define a pixel area, a TFT provided at the crossing of the gate and data lines, a passivation film protecting the TFT, a pixel electrode partially overlapped by the TFT, a gate pad connected to the gate line, and a data pad connected to the data line. The gate line, the gate and data pads, and the pixel electrode include a transparent conductive material. A gate metal material is on the transparent conductive material where the TFT partially overlaps the pixel electrode. The passivation film over the gate and data pads is removed to expose the transparent conductive material included within the gate and data pads.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: January 23, 2007
    Assignee: LG.Philips LCD Co., Ltd
    Inventors: Byung Chul Ahn, Soon Sung Yoo, Oh Nam Kwon, Youn Gyoung Chang, Heung Lyul Cho, Seung Hee Nam, Jae Young Oh
  • Patent number: 7164159
    Abstract: An LED package includes a substrate, internal electrodes provided in an even (2n) number and formed on an upper surface of the substrate, external electrodes provided in the even (2n) number, formed on at least a part of surfaces of the substrate other than the upper surface of the substrate, and electrically connected to the corresponding internal electrodes, and LEDs provided in the even (2n) number, located on the upper surface of the substrate, and provided with an anode and a cathode. The anodes and cathodes of the LEDs are electrically connected to the internal electrodes such that the anode of each of the LEDs is connected to the anode of a neighboring one of the LEDs and the cathode of each of the LEDs is connected to the cathode of another neighboring one of the LEDs.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: January 16, 2007
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Joung Uk Park, Seoung Ju Moon, Seung Hwan Choi
  • Patent number: 7160744
    Abstract: The present invention relates to a fabrication method of LEDs incorporating a step of surface-treating a substrate by a laser and an LED fabricated by such a fabrication method. The present invention can use a laser in order to implement finer surface treatment to an LED substrate over the prior art. As a result, the invention can improve the light extraction efficiency of an LED while protecting the substrate from chronic problems of the prior art such as stress or defects induced from chemical etching and/or physical polishing.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: January 9, 2007
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ho Park, Hun Joo Hahm, Kun Yoo Ko, Hyo Kyong Cho
  • Patent number: 7157748
    Abstract: A nitride-based semiconductor device includes a first semiconductor layer consisting essentially of a nitride-based semiconductor, and a second semiconductor layer disposed on the first semiconductor layer and consisting essentially of a non-doped or first conductivity type nitride-based semiconductor. The first and second semiconductor layers forms a hetero-interface. A gate electrode is disposed on the second semiconductor layer. First and second trenches are formed in a surface of the second semiconductor layer at positions sandwiching the gate electrode. Third and fourth semiconductor layers of the first conductivity type are respectively formed in surfaces of the first and second trenches and each consist essentially of a diffusion layer having a resistivity lower than the first and second semiconductor layers. Source and drain electrodes are electrically connected to the third and fourth semiconductor layers, respectively.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: January 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura
  • Patent number: 7157745
    Abstract: In accordance with the invention, an illumination device comprises a substrate having a surface and a cavity in the surface. At least one light emitting diode (“LED”) is mounted within the cavity, and a monolayer comprising phosphor particles overlies the LED. The phosphor monolayer is adhered to the LED by a monolayer of transparent adhesive material. An optional optical thick layer of transparent material overlies the phosphor monolayer to encapsulate the LED and optionally to form a lens. Methods and apparatus for efficiently making the devices are disclosed.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: January 2, 2007
    Inventors: Greg E. Blonder, Edmar M. Amaya
  • Patent number: 7151046
    Abstract: A surface roughness of a polycrystalline semiconductor film to be formed by a laser annealing method is reduced. A transmittance distribution filter is disposed at the optical system of a laser annealing apparatus. The transmittance distribution filter controls an irradiation light intensity distribution along a scanning direction of a substrate formed with an amorphous silicon semiconductor thin film to have a distribution having an energy part equal to or higher than a fine crystal threshold on a high energy light intensity side and an energy part for melting and combining only a surface layer. This transmittance distribution filter is applied to an excimer laser annealing method, a phase shift stripe method or an SLS method respectively using a general line beam to thereby reduce the height of protrusions on a polycrystalline surface.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: December 19, 2006
    Assignee: Hitachi Displays, Ltd.
    Inventors: Kazuo Takeda, Takeshi Sato, Masakazu Saito, Jun Gotoh
  • Patent number: 7148521
    Abstract: A semiconductor light emitting device comprises: a substrate having first and second major surfaces; a light emitting layer provided in a first portion on the first major surface of the substrate; a first electrode provided above the light emitting layer; a second electrode provided in a second portion on the first major surface of the substrate, the second portion being different from the first portion; and a protrusion provided on the second major surface of the substrate, the protrusion having a planar shape that reflects a planar shape of a light emitting area of the light emitting layer, the light emitting area being sandwiched between the first electrode and the second electrode and facing the protrusion.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: December 12, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidefumi Yasuda, Yuko Kato, Kazuyoshi Furukawa