Abstract: A method of analyzing a circuit comprising a plurality of interconnects is disclosed herein. The method may comprise analyzing at least one electrical property associated with a first interconnect, wherein the first interconnect has at least one first physical dimension. The electrical property may then be stored. A second interconnect having the at least one first physical dimension may then be located and the at least one electrical property is applied to the second interconnect.

Abstract: The irregularities of characteristics of a pair of transistors, which are prepared by a pseudo single crystallizing technique, are reduced. To achieve this, semiconductor layers are formed on a substrate and have pseudo single crystal regions therein, and a plurality of thin film transistors are arranged inside of the pseudo single crystal regions. Two or more of the plurality of thin film transistors, which are required to exhibit small irregularities relative to each other as characteristics thereof, have the direction of the length of the gates of the respective thin film transistors arranged at an inclination of within ±20 degree with respect to the longitudinal direction of the strip-like grown crystals, and they are arranged such that, when channel regions of respective thin film transistors are imaginarily extended in parallel to the growth direction of the strip-like grown crystals, at least portions of the channel regions are superposed on each other.

Abstract: Organic polymers for use in electronic devices, wherein the polymer includes repeat units of the formula: wherein: each R1 is independently H, an aryl group, Cl, Br, I, or an organic group that includes a crosslinkable group; each R2 is independently H, an aryl group or R4; each R3 is independently H or methyl; each R5 is independently an alkyl group, a halogen, or R4; each R4 is independently an organic group that includes at least one CN group and has a molecular weight of about 30 to about 200 per CN group; and n=0–3; with the proviso that at least one repeat unit in the polymer includes an R4. These polymers are useful in electronic devices such as organic thin film transistors.

Abstract: When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III–V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III–V compound semiconductor substrate composed of a first region in form of a crystal having a first average dislocation density and a plurality of second regions having a second average dislocation density higher than the first average dislocation density and periodically aligned in the first region, device regions are defined on the nitride III–V compound semiconductor substrate such that the device regions do not substantially include second regions, emission regions or active regions of devices finally obtained do not include second regions.

Abstract: A MOSFET structure utilizing strained silicon carbon alloy and fabrication method thereof. The MOSFET structure includes a substrate, a graded SiGe layer, a relaxed buffer layer, a strained silicon carbon alloy channel layer, a gate dielectric layer, a polysilicon gate electrode (or metal gate electrode) and a source/drain region.

Abstract: In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material.

Abstract: A first wiring part in a first wiring layer is a starting terminal that is connected to a ground potential. The first wiring part and a second wiring part in a second wiring layer are connected by a first connecting part. The second wiring part and a third wiring part in a third wiring layer are connected by a second connecting part. A fourth wiring part continuously connected with the third wiring part and a fifth wiring part in the second wiring layer are connected by a third connecting part. The fifth wiring part and a sixth wiring part in the first wiring layer are connected by a fourth connecting part. A conducting path that is continuously connected from the starting terminal to an output end is formed by connecting a mound-shaped conducting path thus formed.

Abstract: Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.

Abstract: A light-emitting semiconductor device provides an active layer which comprises thirteen (13) layers that includes six (6) pairs of quantum barrier layers made of Al0.95In0.05N and quantum well layers made of Al0.70In0.30N, which are laminated together alternately. The semiconductor device may also comprise a quantum well layer having a high composition ratio of indium (In). Forming the quantum barrier layer and the quantum well layer to have a high composition ratio of indium (In) increases the lattice constant of the active layer of the semiconductor device.

Abstract: A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

Abstract: A solid-state image pickup device includes, in a substrate, a plurality of photoelectric conversion regions for subjecting incoming light to photoelectric conversion, a reading gate for reading a signal charge from the photoelectric conversion regions, and a transfer register (vertical register) for transferring the signal charge read by the reading gate. Therein, a groove is formed on the surface side of the substrate, and the transfer register and the reading gate are formed at the bottom part of the groove. With such a structure, in the solid-state image pickup device, reduction can be achieved for the smear characteristics, a reading voltage, noise, and others.

Abstract: A first or primary field effect transistor (“FET”) is separated from a body contact thereto by one or more second FETs that are placed electrically in parallel with the first FET. In this way, the body of the first FET can be extended into the region occupied by the second FET to allow contact to be made to the body of the first FET. In one embodiment, the gate conductor of the first FET and a gate conductor of the second FET are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.

Abstract: The present invention is directed to a highly reliable optical semiconductor device (1), which comprises an optical semiconductor chip (2) sealed in a surrounding soft resin (3) and in a hard resin (4) harder than the soft resin. The hard resin (4) has an aperture (7b) configured to relieve a state of hermetic sealing for the soft resin (3) and formed in a direction that imposes no optical influence on a function of the optical semiconductor chip (2). The soft resin (3) and the hard resin (4) are employed for double sealing to form the highly reliable optical semiconductor device (1) without providing any space. This is effective to solve a problem caused in a conventional optical semiconductor device associated with double sealing by soft and hard resins to increase reliability, which requires a space between both resins and results in deteriorated performance, for example, a reduced amount of light.

Abstract: CMOS image sensors and methods for fabricating the same are disclosed. A disclosed CMOS image sensor comprises: a semiconductor substrate; a photo diode; a microlens located over the photo diode; and a color filter layer located over the microlens.

Abstract: A semiconductor memory device comprises a substrate; a first semiconductor layer of a first conduction type having a single crystalline structure isolated from the substrate by an insulator layer; a plurality of memory transistors, each having a gate electrode connected to a word line, a pair of impurity regions of a second conduction type serving as a drain region and a source region formed in the first semiconductor layer, and a channel body of the first conduction type formed in the first semiconductor layer between the impurity regions, and operative to store data as a state of majority carriers accumulated in the channel body; a plurality of device isolation regions formed to isolate memory transistors having gate electrodes commonly connected to the same word line from each other among the plurality of memory transistors; and a plurality of impurity region isolation regions formed to isolate adjacent drain regions from each other and adjacent source regions from each other, the impurity region isolation

Abstract: There are provided an organic bistable element, which is simple in structure, can eliminate the need to increase production process steps, and has a low switching voltage, a memory device using the same, and a method for driving the organic bistable element and the memory device. The organic bistable element having a laminate structure comprises a laminate interposed between a first electrode and a second electrode, the laminate comprising two or more layers of organic thin film which are each dielectric and are different from each other in electrical conductivity. The two or more layers of organic thin film have been stacked on top of each other through an electrically conductive thin film.

Abstract: An antifuse device is constructed from a bipolar junction transistor (BJT). The BJT includes a collector, a base, and an emitter. In one embodiment the BJT is formed inherently within a field effect transistor (FET), including a first doped region, a second doped region, a gate, and a body region. The collector of the BJT is realized by the first doped region of the FET, the emitter of the BJT is realized by the second doped region of the FET, and the base of the BJT is realized by the body region. A high resistance path exists between the collector and the base. A first input voltage is connected to the collector and a second input voltage is connected to the base. A switch connects the emitter to a fixed potential when the switch is closed.

Abstract: The present invention is a semiconductor structure for light emitting devices that can emit in the red to ultraviolet portion of the electromagnetic spectrum. The semiconductor structure includes a Group III nitride active layer positioned between a first n-type Group III nitride cladding layer and a second n-type Group III nitride cladding layer, the respective bandgaps of the first and second n-type cladding layers being greater than the bandgap of the active layer. The semiconductor structure further includes a p-type Group III nitride layer, which is positioned in the semiconductor structure such that the second n-type cladding layer is between the p-type layer and the active layer. The semiconductor structure is built upon a silicon carbide substrate.

Abstract: A light emitting device includes a substrate, a textured layer overlying the substrate, at least one III-nitride layer overlying the textured layer, and a substantially planar light emitting region. Devices incorporating scattering layers may be formed by several different methods. In a first method, an epitaxial layer is deposited then etched to form the textured layer. In a second method, a photomask is deposited and patterned to create openings in the photomask. The textured layer is then preferentially deposited in the openings formed in the photomask. In a third method, the textured layer is deposited under conditions that favor three-dimensional growth, then optionally annealed.

Abstract: According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.