Abstract: A probe unit comprises a flexible substrate made of an inorganic substance and having an almost straight edge, an electro conductive film formed on a surface of the substrate and having a plurality of contact parts aligned on a surface of the edge and can contact with electrodes of a sample and lead parts connected to the contact parts, wherein the substrate is elastically deformed together with the contact part while the plurality of the contacts parts are supported by the edge when a force is added to press a surface of the contact part.

Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/mesa such that layer different from the first Group III nitride compound semiconductor layer 31 is exposed at the bottom portion of the trench. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, laterally, with a top surface of the mesa and a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. Etching may be performed until a cavity portion is provided in the substrate.

Abstract: According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes being controlled by a control signal which is input between the control electrode and the second main electrode; and a capacitor formed by providing an insulating layer between the second main electrode and the control electrode of the semiconductor element.

Abstract: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness.

Abstract: A processing device embodied in an integrated circuit may be divided into first and second functional units. A mount for the integrated circuit may be assigned to the first functional unit, which may define the external electrical connections of the processing device. Processing may take place in a second functional unit of the processing device, whose essential connections may normally be accessible from outside via the external connections of the first functional unit. The processor device having first and second functional units in a mount may be similar to a hybrid circuit but may serve a different purpose. The first functional unit, which may also comprise more than one monolithic integrated circuit, may define the external connections and may make available suitable matching circuits for the second functional unit.

Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.

Abstract: The main object is to provide a manufacturing method of organic semiconductor, an organic semiconductor device structure manufactured by the manufacturing method and an organic semiconductor device, those having uniform and high carrier transport property over a relatively large area.

Abstract: A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film 103 disposed on a quartz substrate 101. A crystal silicon film 105 is obtained by this heat treatment. Then, a oxide film 106 is formed by wet oxidation. At this time, the nickel element is gettered to the oxide film 106 by an action of fluorite. Then, the oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: A semiconductor quantum dot device converts spin information to charge information utilizing an elongated quantum dot having an asymmetric confining potential along its length so that charge movement occurs during orbital excitation. A single electron sensitive electrometer is utilized to detect the charge movement. Initialization and readout can be carried out rapidly utilizing RF fields at appropriate frequencies.

Abstract: An InGaN active layer is formed on a sapphire substrate. A p-side electrode is formed on the InGaN active layer to supply an electric current to this InGaN active layer. The p-side electrode includes {circle around (1)} an Ni layer for forming an ohmic contact with a p-GaN layer, {circle around (2)} an Mo layer having a barrier function of preventing diffusion of impurities, {circle around (3)} an Al layer as a high-reflection electrode, {circle around (4)} a Ti layer having a barrier function, and {circle around (5)} an Au layer for improving the contact with a submount on a lead frame. The p-side electrode having this five-layered structure realizes an ohmic contact and high reflectance at the same time.

Abstract: A method for computing using a quantum system comprising a plurality of superconducting qubits is provided. Quantum system can be in any one of at least two configurations including (i) an initialization Hamiltonian H0 and (ii) a problem Hamiltonian HP. The plurality of superconducting qubits are arranged with respect to one another, with a predetermined number of couplings between respective pairs of superconducting qubits in the plurality of qubits, such that the plurality of superconducting qubits, coupled by the predetermined number of couplings, collectively define a computational problem to be solved. In the method, quantum system is initialized to the initialization Hamiltonian HO. Quantum system is then adiabatically changed until it is described by the ground state of the problem Hamiltonian HP. The quantum state of quantum system is then readout thereby solving the computational problem to be solved.

Abstract: Provided are a vertical carbon nanotube field effect transistor (CNTFET) and a method of manufacturing the same. The method includes: forming a first electrode on a substrate; forming a stack of multiple layers (“multi-layer stack”) on the first electrode, the multiple layers including first and second buried layers and a sacrificial layer interposed between the first and second buried layers; forming a vertical well into the multi-layer stack; growing a CNT within the well; forming a second electrode connected to the CNT on the multi-layer stack into which the well has been formed; forming a protective layer on the second electrode; removing the sacrificial layer and exposing the CNT between the first and second buried layers; forming a gate insulating layer on the exposed surface of the CNT; and forming a gate enclosing the CNT on the gate insulating layer.

Abstract: A compound semiconductor device has: a substrate; a GaN channel layer; an n-type AlqGa1?qN (0<q?1) electron supply layer; an n-type GaN cap layer; a gate electrode disposed on the cap layer and forming a Schottky contact; recesses formed on both sides of the gate electrode on source and drain sides by at least partially removing the cap layer, the recesses having a bottom surface of a roughness larger than a roughness of a surface of the cap layer under the gate electrode; a source electrode disposed on the bottom surface of the recess on the source side; and a drain electrode disposed on the bottom surface of the recess on the drain side.

Abstract: A semiconductor device including a transistor having an SOI structure the operating speed of which is not affected is provided. A MOS transistor having the SOI structure is formed which satisfies R·C·f<1 where C is a gate capacitance (F), R is a body resistance (?), f is a clock operating frequency (Hz), and f?500 MHz.

Abstract: A semiconductor device including an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.

Abstract: The invention relates to a semiconductor structure for use in the near infrared region, preferably in the range from 1.3 to 1.6 ?m, said structure comprising an active zone consisting of a plurality of epitaxially grown alternating layers of Si and Ge, a base layer of a first conductivity type disposed on one side of said active zone, and a cladding layer of the opposite conductivity type to the base layer, the cladding layer being provided on the opposite side of said active zone from said base layer, wherein the alternating Si and Ge layers of said active zone form a superlattice so that holes are located in quantized energy levels associated with a valance band and electrons are localized in a miniband associated with the conduction band and resulting from the superlattice structure. The invention is also directed to a method of manufacturing aforementioned structure.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such apparatus and methods may include identifying a first quantum state of a lattice having a system of quasi-particles disposed thereon, moving the quasi-particles within the lattice according to at least one predefined rule, identifying a second quantum state of the lattice after the quasi-particles have been moved, and determining a computational result based on the second quantum state of the lattice.

Abstract: This invention relates to an electronic element having an electron function which acts even at room temperature using a super dielectric effect. The element has a crystalline electron system, and uses a perovskite crystal in the ground state of a “macroscopic quantum effect” which occurs when the electron number is defined, or nearly defined. The electronic element used in an electric field such that the two-dimensional plane of doped crystals ground state of a “fractional quantum Hall effect” wherein the doping amount of the crystals is 0.05 or less, or if localization is introduced, 0.6 or less, and the crystals may have a doping amount variation determined by the degree of localization.

Abstract: A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.

Abstract: Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a semiconductor device with the resistor pattern. Embodiments of the invention also provide a semiconductor device with a resistor pattern that is formed narrower than the minimum line width that can be defined in a photolithographic process so that sheet resistance thereof increases, and a method of fabricating the same.