Patents by Inventor C. Lin

C. Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170120386
    Abstract: The present disclosure relates to aluminum-based products having 1-30 vol. % of a ceramic phase. The aluminum alloy products may be produced via additive manufacturing techniques to facilitate production of the aluminum-based products having the 1-30 vol. % of the ceramic phase.
    Type: Application
    Filed: December 1, 2016
    Publication date: May 4, 2017
    Inventors: Jen C. Lin, Lynnette M. Karabin, Cagatay Yanar, David W. Heard
  • Publication number: 20170120393
    Abstract: The present disclosure relates to aluminum-based products having 1-30 vol. % of a ceramic phase. The aluminum alloy products may be produced via additive manufacturing techniques to facilitate production of the aluminum-based products having the 1-30 vol. % of the ceramic phase.
    Type: Application
    Filed: December 1, 2016
    Publication date: May 4, 2017
    Inventors: Jen C. Lin, Lynnette M. Karabin, Cagatay Yanar, David W. Heard, Gen Satoh
  • Publication number: 20170121795
    Abstract: New wrought 7xxx aluminum alloys are disclosed. The new wrought 7xxx aluminum alloys generally include from 3.75 to 8.0 wt. % Zn, from 1.25 to 3.0 wt. % Mg, where the wt. % Zn exceeds the wt. % Mg, from 0.35 to 1.35 wt. % Cu, from 0.04 to 0.20 wt. % V, from 0.06 to 0.20 wt. % Zr, where V+Zr?0.23 wt. %, from 0.01 to 0.25 wt. % Ti, up to 0.50 wt. % Mn, up to 0.40 wt. % Cr, up to 0.35 wt. % Fe, and up to 0.25 wt. % Si, the balance being aluminum and impurities, wherein the wrought 7xxx aluminum alloy include not greater than 0.10 wt. % each of any one impurity, and wherein the wrought 7xxx aluminum alloy includes not greater than 0.35 wt. % in total of the impurities.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 4, 2017
    Inventors: Xinyan Yan, James Daniel Bryant, Jen C. Lin, Wenping Zhang, Eider Simielli
  • Patent number: 9640518
    Abstract: The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by forming through openings that extend through a metallic carrier between first and second surfaces of the metallic carrier, attaching a chip-on-interposer subassembly on the metallic carrier using an adhesive, with the chip inserted into a cavity of the metallic carrier, and with the chip-on-interposer subassembly attached to the metallic carrier, forming first and second buildup circuitry on a first surface of the interposer and the second surface of the metallic carrier, respectively, and subsequently forming plated through holes that extend into the through openings to provide electrical and thermal connections between the first and second buildup circuitry. The method and resulting device advantageously provides vertical signal routing and stacking capability for a semiconductor package.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 2, 2017
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 9629345
    Abstract: A biochemical ball includes a first half, a second half, and a plurality of sponge filters. The first half has a plurality of first ribs, a first rim, and a first partition. The first partition divides the first half into a plurality of equal first accommodating spaces. The first rim of the first half is provided with a first fastener and a connecting joint. The second half has a plurality of second ribs, a second rim, and a second partition. The second partition divides the second half into a plurality of equal second accommodating spaces. The second rim of the second half is provided with a second fastener configured to correspondingly engage with the first fastener. The sponge filters are so received in the first and second accommodating spaces that the sponge filters are separated without contacting each other, thereby enhancing filtering efficiency.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: April 25, 2017
    Inventor: James C. Lin
  • Publication number: 20170095543
    Abstract: Disclosed is a method of treating small intestinal bacterial overgrowth (SIBO) or a SIBO-caused condition in a human subject. SIBO-caused conditions include irritable bowel syndrome, fibromyalgia, chronic pelvic pain syndrome, chronic fatigue syndrome, depression, impaired mentation, impaired memory, halitosis, tinnitus, sugar craving, autism, attention deficit/hyperactivity disorder, drug sensitivity, an autoimmune disease, and Crohn's disease. Also disclosed are a method of screening for the abnormally likely presence of SIBO in a human subject and a method of detecting SIBO in a human subject. A method of determining the relative severity of SIBO or a SIBO-caused condition in a human subject, in whom small intestinal bacterial overgrowth (SIBO) has been detected, is also disclosed.
    Type: Application
    Filed: May 9, 2016
    Publication date: April 6, 2017
    Applicant: Cedars-Sinai Medical Center
    Inventors: Henry C. Lin, Mark Pimentel
  • Publication number: 20170088920
    Abstract: Improved wrought 7xxx aluminum alloy products are disclosed. The improved wrought 7xxx aluminum alloy products generally include 6.0-10.0 wt. % Zn, 1.4-2.2 wt. % Mg, 1.3-2.5 wt. % Cu and 0.080-0.250 wt. % Cr. The improved wrought 7xxx aluminum alloy products generally have a thickness of from 3.0 inches to 12 inches, and realize an improved combination of properties, such an improved combination of crack deviation resistance, strength, fracture toughness and corrosion resistance.
    Type: Application
    Filed: December 12, 2016
    Publication date: March 30, 2017
    Inventors: Julien Boselli, Jen C. Lin, Mark A. James, Gary H. Bray, John R. Brockenbrough
  • Publication number: 20170084530
    Abstract: A wiring board includes a low CTE (coefficient of thermal expansion) and high thermal conductivity isolator incorporated in a resin laminate by an adhesive and a bridging element disposed over the isolator and the resin laminate and electrically coupled to a first routing circuitry on the isolator and a second routing circuitry on the resin laminate. The isolator provides CTE-compensated contact interface for a semiconductor chip to be assembled thereon, and also provides primary heat conduction for the chip. The bridging element offers a reliable connecting channel for interconnecting contact pads on the isolator to terminal pads on the resin laminate.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20170069602
    Abstract: An interconnect substrate having vertical connection channels around a cavity is characterized in that contact pads are exposed from the cavity and the vertical connection channels are made of a combination of metal posts and metallized vias. The cavity includes a recess in a core layer and an aperture in a stiffener. The metal posts, disposed over the top surface of the core layer, are sealed in the stiffener and are electrically connected to a buildup circuitry adjacent to the bottom surface of the core layer. The minimal height of the metal posts needed for the vertical connection can be reduced by the amount equal to the depth of the recess. The buildup circuitry is electrically connected to the metal posts through the metallized vias and provides the contact pads exposed from the cavity for device connection.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 9, 2017
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 9587298
    Abstract: New magnesium-zinc aluminum alloy bodies and methods of producing the same are disclosed. The new magnesium-zinc aluminum alloy bodies generally include 3.0-6.0 wt. % magnesium and 2.5-5.0 wt. % zinc, where at least one of the magnesium and the zinc is the predominate alloying element of the aluminum alloy bodies other than aluminum, and wherein (wt. % Mg)/(wt. % Zn) is from 0.6 to 2.40, and may be produced by preparing the aluminum alloy body for post-solutionizing cold work, cold working by at least 25%, and then thermally treating. The new magnesium-zinc aluminum alloy bodies may realize improved strength and other properties.
    Type: Grant
    Filed: March 9, 2013
    Date of Patent: March 7, 2017
    Assignee: ARCONIC INC.
    Inventors: Jen C. Lin, John M. Newman, Ralph R. Sawtell, Rajeev G. Kamat, Darl G. Boysel, Gary H. Bray, James Daniel Bryant, Brett P. Connor, Mario Greco, Gino Norman Iasella, David J. McNeish, Shawn J. Murtha, Roberto J. Rioja, Shawn P. Sullivan
  • Publication number: 20170062394
    Abstract: A semiconductor assembly includes an encapsulated device and a thermally enhanced device face-to-face mounted together through first and second routing circuitries and a heat spreader that provides thermal dissipation and electromagnetic shielding. The encapsulated device has a first semiconductor chip sealed in an encapsulant, whereas the thermally enhanced device has a second semiconductor chip thermally conductible to a shielding lid of the heat spreader and laterally surrounded by posts of the heat spreader. The first and second semiconductor chips are mounted on two opposite sides of the first routing circuitry, and the second routing circuitry is disposed on the shielding lid and electrically coupled to the first routing circuitry by bumps. The first and second routing circuitries provide staged fan-out routing for the first and second semiconductor chips.
    Type: Application
    Filed: November 16, 2016
    Publication date: March 2, 2017
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20170052961
    Abstract: In one implementation, a method is provided that comprises receiving a plurality of potential listings associated with an entity from a provider system. Each listing comprises a confidence score assigned by the provider system. A representative listing of the entity located on the provider system is designated from amongst the plurality of potential listings based on the confidence score. A first request is transmitted to synchronize the representative listing with the entity on the provider system. Responsive to receiving an indication that the request to synchronize is complete, a second request to suppress remaining listings of the potential listings as duplicates is provided. The remaining listings having confidence scores lower than the confidence score associated with the representative listing. The second request to suppress the remaining listings as duplicate listings is provided to the provider system using an API and a confirmation that the remaining listings are suppressed.
    Type: Application
    Filed: November 3, 2016
    Publication date: February 23, 2017
    Inventors: Howard C. Lerman, Thomas C. Dixon, Kevin Caffrey, David C. Lin
  • Patent number: 9569560
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for dynamically generating indicators of entity locations on an electronic map corresponding, for example, to a suggested search request. In one aspect, a method includes providing an electronic map of a geographic area for display on a user interface, receiving a character string entered into the user interface, the character string representing a partial search query, determining a suggested search request based on the character string, and identifying an entity responsive to the suggested search request and a geographic location for the identified entity. An indicator identifying the geographic location of the entity is provided for display on the electronic map.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: February 14, 2017
    Assignee: GOOGLE INC.
    Inventors: Michelle I-Ching Lee, Jocelyn C. Lin, Keekim Heng
  • Patent number: 9570372
    Abstract: The present invention relates to methods of making a semiconductor assembly having a semiconductor device embedded in a heat spreader and electrically connected to a dual-stage formed interconnect substrate. In a preferred embodiment, the interconnect substrate consists of first and second build-up circuitries and the methods are characterized by the step of attaching a semiconductor subassembly having a first build-up circuitry adhered to a sacrificial carrier to a heat spreader using an adhesive with the semiconductor device inserted into a cavity of the heat spreader and the step of detaching the sacrificial carrier from the first build-up circuitry. The heat spreader provides thermal dissipation, and the first and second build-up circuitries provide staged fan-out routing for the semiconductor device.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 14, 2017
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20170033083
    Abstract: A package-on-package semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between two both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, another semiconductor device is disposed over a top surface of the core base and is electrically coupled to the semiconductor device in the dielectric recess through a buildup circuitry under a bottom surface of the core base.
    Type: Application
    Filed: February 3, 2016
    Publication date: February 2, 2017
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20170034923
    Abstract: A method of making a stackable wiring board is characterized by positioning an electronic component in a dielectric recess to realize the thickness reduction of the wiring board and sidewalls of the recess can confine the dislocation of the electronic component to avoid misalignment between buildup circuitry and the electronic component. An array of metal posts that provide vertical electrical connections are formed by using the same metal carrier that forms the recess, so that the predetermined distance and relative location between metal posts and pads/bumps of the electronic component can be maintained.
    Type: Application
    Filed: December 3, 2015
    Publication date: February 2, 2017
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 9556502
    Abstract: New 6xxx aluminum alloys are disclosed. The new 6xxx aluminum alloys may include 1.05-1.50 wt. Mg, 0.60-0.95 wt. % Si, where the (wt. % Mg)/(wt. % Si) is from 1.30 to 1.90, 0.275-0.50 wt. % Cu, and from 0.05 to 1.0 wt. % of at least one secondary element, wherein the secondary element is selected from the group consisting of V, Fe, Cr, Mn, Zr, Ti, and combinations thereof.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: January 31, 2017
    Assignee: Arconic Inc.
    Inventors: Jen C. Lin, Anton J. Rovito, Timothy P. Doyle, Shawn P. Sullivan, Gabriele F. Ciccola, Christopher J. Tan
  • Publication number: 20170025393
    Abstract: A face-to-face semiconductor assembly is characterized in that an encapsulated device having a first semiconductor chip surrounded by an array of vertical connecting elements in an encapsulant is stacked on and electrically coupled to a thermally enhanced device having a second semiconductor chip accommodated in a cavity of a thermal board. The first and second semiconductor chips are face-to-face mounted on two opposite sides of a first routing circuitry and is further electrically connected to the vertical connecting elements through the first routing circuitry. The thermal board has a heat spreader to provide thermal dissipation for the second semiconductor chip. The first routing circuitry provides primary fan-out routing for the first and second semiconductor chips, whereas the vertical connecting elements provide electrical contacts for next-level connection.
    Type: Application
    Filed: October 8, 2016
    Publication date: January 26, 2017
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 9550005
    Abstract: Embodiments of this disclosure include systems, methods, and kits for sterilizing in vivo catheters using an optical fiber to deliver UV light. In an embodiment, a method for sterilizing a catheter with at least a first lumen, includes inserting a distal end of a fiber optic cable into a fiber insertion port of a catheter connector attached to a hub of the first lumen, flushing the first lumen with fluid from a fluid source, inserting the fiber optic cable into the first lumen until a stopper of the fiber optic cable is adjacent to the fiber insertion port, providing light to the fiber optic cable from a light source after the fiber optic cable is inserted into the first lumen, withdrawing the fiber optic cable from the first lumen while the light is provided, and ceasing to provide light to the fiber optic cable after the fiber optic cable is withdrawn from the first lumen. The disclosure is also applicable to catheters with multiple lumens and to catheters accessed through subcutaneous ports.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: January 24, 2017
    Assignee: Ultraviolet Interventions, Inc.
    Inventors: Roger C Lin, Laurence M Sandell
  • Publication number: 20170018505
    Abstract: A wiring board with embedded component and integrated stiffener is characterized in that an embedded semiconductor device, a first routing circuitry, an encapsulant and an array of vertical connecting elements are integrated as an electronic component disposed within a through opening of a stiffener, and a second routing circuitry is disposed beyond the through opening of the stiffener and extends over the stiffener. The mechanical robustness of the stiffener can prevent the wiring board from warping. The embedded semiconductor device is electrically coupled to the first routing circuitry and surrounded by the vertical connecting elements in electrical connection with the first and second routing circuitries. The first routing circuitry provides primary fan-out routing for another semiconductor device to be assembled on the wiring board, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the electronic component with the stiffener.
    Type: Application
    Filed: October 1, 2016
    Publication date: January 19, 2017
    Inventors: Charles W. C. Lin, Chia-Chung Wang