Patents by Inventor Chang-Lin (Peter) Hsieh

Chang-Lin (Peter) Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369456
    Abstract: A semiconductor device with back-side contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a stack of nanostructured semiconductor layers disposed adjacent to the first S/D region, a gate structure surrounding each of the nanostructured semiconductor layers, a first pair of spacers disposed on opposite sidewalls of the first S/D region, a second pair of spacers disposed on opposite sidewalls of the second S/D region, a third pair of spacers disposed on opposite sidewalls of the gate structure, a first contact structure disposed on a first surface of the first S/D region, and a second contact structure disposed on a second surface of the first S/D region. The first and second surfaces are opposite to each other. The first pair of spacers are disposed on opposite sidewalls of the second contact structure.
    Type: Application
    Filed: March 10, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhi-Chang Lin, Jung-Hung Chang, Shih-Cheng Chen, Chih-Hao Wang, Chien Ning Yao, Tsung-Han Chuang, Kuo-Cheng Chiang
  • Publication number: 20230369469
    Abstract: A method of fabricating a device includes providing a fin having a plurality of channel layers and a plurality of multilayer epitaxial layers interposing the plurality of channel layers. The multilayer epitaxial layers include a first epitaxial layer interposed between second and third epitaxial layers. The first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate. The method further includes laterally etching the first, second, and third epitaxial layers to provide a convex sidewall profile on opposing lateral surfaces of the multilayer epitaxial layers. The method further includes forming an inner spacer between adjacent channel layers. The inner spacer interfaces the convex sidewall profile of the multilayer epitaxial layers along a first inner spacer sidewall surface. The method further includes replacing the multilayer epitaxial layers with a portion of a gate structure.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Shih-Cheng CHEN, Kuo-Cheng CHIANG, Zhi-Chang LIN
  • Publication number: 20230369520
    Abstract: The present disclosure provides a photo sensing device and a method for forming a photo sensing device. The photo sensing device includes a substrate, a photosensitive member, a superlattice layer and a diffusion barrier structure. The substrate includes a silicon layer at a front surface. The photosensitive member extends into and at least partially surrounded by the silicon layer, wherein an upper portion of the photosensitive member protruding from the silicon layer has a top surface and a facet tapering toward the top surface. The superlattice layer is disposed between the photosensitive member and the silicon layer. The diffusion barrier structure is disposed at a first side of the photosensitive member and a bottom of the diffusion barrier structure is at a level below a top surface of the silicon layer, wherein at least a portion of the diffusion barrier structure is laterally surrounded by the silicon layer.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 16, 2023
    Inventors: CHAN-HONG CHERN, WEIWEI SONG, CHIH-CHANG LIN, LAN-CHOU CHO, MIN-HSIANG HSU
  • Publication number: 20230335622
    Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Chang Lin, Bo-Han Huang, Chih-Chung Chen, Chun-Hsien Lin, Shih-Hung Tsai, Po-Kuang Hsieh
  • Publication number: 20230335607
    Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20230330901
    Abstract: Present invention is related to an evenly heating method for enhancing heating result having steps of: introducing a foam material into a mould, compressing the foam material by a mechanical force to a preset thickness or status, and heating the foam material to obtain a foam product. By applying the mechanical force to the foam material during the process, the foam material could be compressed into a more compact status in order to be heated more evenly and thoroughly. The present invention provides the foam product in good quality by a simple and low cost heating method.
    Type: Application
    Filed: April 14, 2022
    Publication date: October 19, 2023
    Inventor: Po-Chang Lin
  • Publication number: 20230335039
    Abstract: A color adjustment device applied to a display panel includes a first controller and a second controller. The first controller is configured to control light emission of the display panel. The second controller is connected to the first controller, and is configured to receive an input image, and determine whether a blue component proportion of the input image is greater than a preset proportion and whether luminance of the display panel is lower than a luminance threshold value, wherein at least one pulse signal is transmitted from the second controller to the first controller through a first signal line when the blue component proportion is greater than the preset proportion and the luminance of the display panel is lower than the luminance threshold value.
    Type: Application
    Filed: August 3, 2022
    Publication date: October 19, 2023
    Inventors: Chang Lin LIOU, Chih Hao LO, Cheng Ta WU
  • Patent number: 11788611
    Abstract: An actuator with a worm gear positioning mechanism, which includes: a shell casing (10); a motor (20) having a worm rod (21); a transmission assembly (30) having a guiding screw rod (31), a worm gear (32) and a bearing (33), the worm gear (32) having an annular member (321) having an inner circumferential surface (322); an outer tube (40) having an outer circumferential surface (41) attached to the inner circumferential surface (322), the worm gear (32) being positioned between the worm rod (21) and the outer tube (40) on a radial direction; and a telescopic tube (50) disposed in the outer tube (40) and having an inner tube (51) and a screw nut (52), the screw nut (52) moveably screwed with the guiding screw rod (31) to make the inner tube (51) linearly movable relative to the outer tube (40).
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: October 17, 2023
    Assignee: TIMOTION TECHNOLOGY CO., LTD.
    Inventor: Yu-Chang Lin
  • Patent number: 11791401
    Abstract: A method of fabricating a device includes providing a fin having a plurality of channel layers and a plurality of multilayer epitaxial layers interposing the plurality of channel layers. The multilayer epitaxial layers include a first epitaxial layer interposed between second and third epitaxial layers. The first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate. The method further includes laterally etching the first, second, and third epitaxial layers to provide a convex sidewall profile on opposing lateral surfaces of the multilayer epitaxial layers. The method further includes forming an inner spacer between adjacent channel layers. The inner spacer interfaces the convex sidewall profile of the multilayer epitaxial layers along a first inner spacer sidewall surface. The method further includes replacing the multilayer epitaxial layers with a portion of a gate structure.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Kuo-Cheng Chiang, Zhi-Chang Lin
  • Patent number: 11790147
    Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may further include dynamically updating the routing graph at a graphical user interface, based upon, at least in part, a creation of a routing segment or a via at the graphical user interface.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: October 17, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hongzhou Liu, Rahaprian Premavathi Mudiarasan, Sandipan Ghosh, Hui Xu, Chris (Shyh-Chang) Lin, Joshua Baudhuin, Ron Pyke, Juno Lin, Allen You, Yu Liu, Jiulong Zhang, Thomas Richards
  • Publication number: 20230327692
    Abstract: A chip comprises a plurality of signal receiving circuits, a transceiver circuit and a memory circuit. The plurality of signal receiving circuits are set at different locations on the chip. The transceiver circuit includes a dynamic switch circuit and a baseband processor. The dynamic switch circuit is configured to output a to-be-analyzed signal from the one of the plurality of signal receiving circuits. The baseband processor is configured to obtain a frequency spectrum and magnitude of the to-be-analyzed signal, and obtain a data packet of an input radio-frequency signal received by an external antenna. The memory circuit is configured to store the frequency spectrum and magnitude of the to-be-analyzed signal, and transmit the frequency spectrum and magnitude to an external computing device, so as to determine an interference path, an interference source or a combination thereof of an interference signal of the transceiver circuit through the external computing device.
    Type: Application
    Filed: October 16, 2022
    Publication date: October 12, 2023
    Inventor: Chung Chang LIN
  • Patent number: 11784437
    Abstract: A card connector includes a transmission conductor assembly that includes a backup transmission conductor, a first signal transmission conductor, an inspection signal transmission conductor, a first grounding transmission conductor, a command reset transmission conductor, a first differential transmission conductor, a second differential transmission conductor, a second grounding transmission conductor, a third grounding transmission conductor, a fourth grounding transmission conductor, a first power transmission conductor, a second power transmission conductor, a third differential transmission conductor, a fourth differential transmission conductor, a second signal transmission conductor, a fifth grounding transmission conductor, a sixth grounding transmission conductor, a seventh grounding transmission conductor, a fifth differential transmission conductor, a sixth differential transmission conductor, and a write-protection transmission conductor, each of which has two ends respectively forming a spring se
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: October 10, 2023
    Assignee: V-GENERAL TECHNOLOGY CO., LTD.
    Inventors: Po-Wen Yeh, Hsuan Ho Chung, Yung-Chang Lin, Yu Hung Lin, Tzu-Wei Yeh, Yu-Lun Yeh
  • Publication number: 20230320040
    Abstract: A cooling apparatus is provided. An external cooling fluid flows into an external inlet opening from an external inlet pipe and passes through a heat exchanger to flow out of an external outlet opening to an external outlet pipe. An internal cooling fluid flows into an internal inlet pipe from the server and flows into an internal inlet opening from the internal inlet pipe and passes through the heat exchanger for heat exchange with the external cooling fluid to flow out of an internal outlet opening to an internal outlet pipe. A hot-swap pump has a pump main body, an inlet anti-leakage pipe, an outlet anti-leakage pipe and a hot-swap connector. The inlet anti-leakage pipe includes an inlet connector and an inlet anti-leakage valve. The outlet anti-leakage pipe includes an outlet connector and an outlet anti-leakage valve. The hot-swap connector is electrically connected to the pump main body.
    Type: Application
    Filed: April 5, 2022
    Publication date: October 5, 2023
    Applicant: Super Micro Computer, Inc.
    Inventors: Chia-Wei CHEN, Te-Chang LIN, Yueh-Ming LIU, Yu-Hsiang HUANG, Ya-Lin LIU, Chi-Che CHANG
  • Publication number: 20230317724
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.
    Type: Application
    Filed: June 2, 2023
    Publication date: October 5, 2023
    Inventors: Zhi-Chang Lin, Huan-Chieh Su, Kuo-Cheng Chiang
  • Publication number: 20230314719
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
  • Patent number: 11776911
    Abstract: A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ming Chen, Yu-Chang Lin, Chung-Ting Li, Jen-Hsiang Lu, Hou-Ju Li, Chih-Pin Tsao
  • Patent number: 11776494
    Abstract: A backlight driving method includes steps of: (A) receiving a piece of image data that includes a number (K) of segments, where K?2; (B) generating a piece of adjustment data that includes a number (K) of segments; each segment of the adjustment data being generated based on a respective segment of the image data and upon receipt of the respective segment of the image data; (C) generating, based on a piece of delay data and on an original synchronization control (SC) signal that has a pulse, an internal SC signal that has a number (K) of pulses; and (D) generating a backlight driving output based on the adjustment data and the internal SC signal, so as to drive a backlight source of a scan-type display to emit light.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: October 3, 2023
    Assignee: MACROBLOCK, INC.
    Inventors: Chang-Lin Chen, Chun-Yi Li, Wei-Chung Chen
  • Patent number: 11776961
    Abstract: A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu
  • Publication number: 20230308206
    Abstract: An optical device includes a first waveguide, ring-shaped waveguides adjacent to the first waveguide, and heaters coupled to the ring-shaped waveguides in one-to-one correspondence. A method includes coupling a first light source with a first wavelength to the first waveguide, increasing electric current through the heaters until a first one of the ring-shaped waveguides resonates, assigning the first one of the ring-shaped waveguides to the first wavelength, resetting the electric current through the heaters to the initial electric current, coupling a second light source with a second wavelength to the first waveguide wherein the second wavelength is different from the first wavelength, increasing the electric current through the heaters until a second one of the ring-shaped waveguides resonates wherein the second one of the ring-shaped waveguides is different from the first one of the ring-shaped waveguides, and assigning the second one of the ring-shaped waveguides to the second wavelength.
    Type: Application
    Filed: August 16, 2022
    Publication date: September 28, 2023
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Stefan Rusu, Weiwei Song, Lan-Chou Cho
  • Publication number: 20230307385
    Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan