Abstract: A method for manufacturing a memory device includes forming a first metal layer over a substrate, forming a magnetic tunnel junction (MTJ) layer stack over the first metal layer, forming a second metal layer over the MTJ layer stack, forming a hard mask layer over the second metal layer, performing a first etching process on the MTJ layer stack to form an MTJ structure and a redeposited layer on a sidewall of the MTJ structure, performing a second etching process to remove the redeposited layer, and performing a third etching process on the sidewall of the MTJ structure.

Abstract: A system for poisoned data management includes an interface and a processor. The interface is configured to receive an indication of poisoned data in a published event. The processor is configured to mark the poisoned data in a data graph; mark in the data graph a set of downstream nodes as poisoned; and store the data graph.

Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

Abstract: An electronic device for removing a to-be-removed object on a device under test (DUT) is provided. The electronic device includes a working platform, an identification unit and a removal unit. The working platform carries the DUT. The identification unit is arranged above the working platform for acquiring position information of the to-be-removed object. The removal unit is coupled to the identification unit, and the removal unit includes a removal element. The removal element removes the to-be-removed object according to the position information. The removal element has a ring structure and a confinement space, wherein the ring structure is connected with the confinement space and the confinement space faces the working platform.

Abstract: The disclosure is a nut structure for an electric pushing rod. The electric pushing rod has a guide screw (A) with an outer thread (A1). The nut structure includes a metal cylinder (10) and a plastic intermediate component (20). The metal cylinder (10) has a pivot hole (11) being passed through by the guide screw (A). An inner wall of the pivot (11) is provided with an inner thread (12). The plastic intermediate component (20) covers the inner thread (12) and is disposed of between the outer thread (A1) and the inner thread (12). The plastic intermediate component (20) includes a fixed side thread (21) mounted on the inner thread (12) and a driving side thread (22) screwed with the outer thread (A1). Therefore, the strength may be enhanced to avoid both the nut structure from being broken and the driving side thread (22) from getting stripped.

Abstract: A semiconductor device package includes a first substrate, a second substrate, a conductive structure, a first solder and a second solder. The second substrate is disposed over the first substrate. The conductive structure is disposed between the first substrate and the second substrate. The conductive structure includes a first wetting portion, a second wetting portion, and a non-wetting portion disposed between the first wetting portion and the second wetting portion. The first solder covers the first wetting portion and connects the conductive structure to the first substrate. The second solder covers the second wetting portion and connects the conductive structure to the second substrate. The first solder is spaced apart from the second solder by the non-wetting portion.

Abstract: A module connector comprising a first connecting component and a second connecting component. The first connecting component includes a first base, a plurality of first conductors and a plurality of first clamping parts. The first base includes a first body, a plurality of first cable grooves, a plurality of first through holes and a plurality of third cable grooves. The first body forms the first cable grooves and the third cable grooves to be able to accommodate the cables. The central axes of the first through holes are at a first angle with the first cable grooves and pass through the first body, and one ends of the first through holes communicate with the first cable grooves. The first conductors are disposed in the first cable grooves. The second connecting component can connect with the first connecting component through the cables, so that at least one of signals and power can be transmitted between the second connecting component and the circuit board.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures stacked in a vertical direction over a substrate, and a first dummy fin structure between the first nanostructures and the second nanostructures. The semiconductor device structure includes a first gate structure formed over the first nanostructures, wherein the first gate structure includes a gate dielectric layer, and the gate dielectric layer is in direct contact with a sidewall surface of the first dummy fin structure.

Abstract: A backlight driving method includes steps of: (A) generating an original synchronization control (SC) signal, and a serial input signal that contains multiple predetermined delay values; (B) generating multiple internal SC signals based on the original SC signal and the delay values, such that respective time delays of the internal SC signals with respect to the original SC signal are respectively dependent on the delay values; and (C) generating multiple backlight driving outputs based on the internal SC signals to respectively drive multiple backlight sources, such that the backlight sources emit light in an order dependent on the delay values.

Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.

Abstract: This disclosure provides a test kit for testing a device under test (DUT) including a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having a nest and an interposer substrate installed under the nest.

Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

Abstract: A memory system having multiple address tables to translate logical addresses to physical addresses at different granularity levels is disclosed. For example, a first address table is associated with a first block size of translating logical addresses for accessing system files and application files; and a second address table is associated with a second block size of translating logical addresses for storing and/or retrieving data from an image sensor of a surveillance camera. A user interface can be used to access a configuration option to specify the second block size; and a user may indicate a typical size of an image or video file to be recorded by the surveillance camera to calculate the second block size and thus configure the second address table for a partition to record the image or video files.

Abstract: A semiconductor device package includes a substrate, a first solder paste, an electrical contact and a first encapsulant. The substrate includes a conductive pad. The first solder paste is disposed on the pad. The electrical contact is disposed on the first solder paste. The first encapsulant encapsulates a portion of the electrical contact and exposes the surface of the electrical contact. The electrical contact has a surface facing away from the substrate. A melting point of the electrical contact is greater than that of the first solder paste. The first encapsulant includes a first surface facing toward the substrate and a second surface opposite to the first surface. The second surface of the first encapsulant is exposed to air.

Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.

Abstract: A leg structure of an electric table includes a pair of support assemblies (10), multiple horizontal rods (20) and a pair of drive assemblies (30). The support assemblies (10) are arranged spacedly and parallelly to each other. Each support assembly (10) includes a connecting rod (11) and a pair of telescopic posts (12). Each telescopic post (12) is connected and fixed to the connecting rod (11). Each horizontal rod (20) is separately connected to each support assembly (10) and is parallel to each other. Each drive assembly (30) is separately received in each support assembly (10) for driving each telescopic post (12) to ascend or descend. Therefore, the leg structure of an electric table may be easily assembled and the whole structure is stable.

Abstract: A lightweight beam structure includes a first and a second frame. The first frame includes an upper plate, two inner side plates downward bent and extended from two sides of the upper plate, two outer side plates upward bent and extended from two inner side plates respectively and two fixing plates bent and extended from two outer side plates respectively. Each outer side plate is formed outside each inner side plate. A groove is formed between each inner side plate and each outer side plate. The second frame is connected with the first frame and includes a top plate and two intermediate plates downward bent and extended from two sides of the top plate. Each intermediate plate is received in each groove. The top plate is formed over the upper plate. Therefore, the stability is maintained and the weight is reduced so that the material costs may be decreased.

Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.