Abstract: A lithography system is provided capable of deterring contaminants, such as tin debris from entering into the scanner. The lithography system in accordance with various embodiments of the present disclosure includes a processor, an extreme ultraviolet light source, a scanner, and a hollow connection member. The light source includes a droplet generator for generating a droplet, a collector for reflecting extreme ultraviolet light into an intermediate focus point, and a light generator for generating pre-pulse light and main pulse light. The droplet generates the extreme ultraviolet light in response to the droplet being illuminated with the pre-pulse light and the main pulse light. The scanner includes a wafer stage. The hollow connection member includes an inlet that is in fluid communication with an exhaust pump. The hollow connection member provides a hollow space in which the intermediate focus point is disposed.

Abstract: A package includes an electronic die, a photonic die underlying and electronically communicating with the electronic die, a lens disposed on the electronic die, and a prism structure disposed on the lens and optically coupled to the photonic die. The prism structure includes first and second polymer layers, the first polymer layer includes a first curved surface concaving toward the photonic die, the second polymer layer embedded in the first polymer layer includes a second curved surface substantially conforming to the first curved surface, and an outer sidewall of the second polymer layer substantially aligned with an outer sidewall of the first polymer layer.

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die, an insulating encapsulation, and a plurality of conductive pillars. The second semiconductor die is located on and electrically communicates to the first semiconductor die through joints therebetween. The insulating encapsulation encapsulates the first semiconductor die and the second semiconductor die and covers the joints. The plurality of conductive pillars is next to and electrically connected to the first semiconductor die and the second semiconductor die, and is covered by the insulating encapsulation.

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

Abstract: A probe card device and a self-aligned probe are provided. The self-aligned probe includes a fixing end portion configured to be abutted against a space transformer, a testing end portion configured to detachably abut against a device under test (DUT), a first connection portion connected to the fixing end portion, a second connection portion connected to the testing end portion, and an arced portion that connects the first connection portion and the second connection portion. The fixing end portion and the testing end portion jointly define a reference line passing there-through. The first connection portion has an aligned protrusion, and a maximum distance between the arced portion and the reference line is greater than 75 ?m and is less than 150 ?m.

Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

Abstract: The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.

Abstract: A current load circuit for testing a power supply circuit includes a control circuit and a load generation circuit. The control circuit is configured to generate a reset signal according to a clock signal. The load generation circuit is coupled to the control circuit and has several load configurations. The load generation circuit is configured to provide one of the load configurations as a current load of the load generation circuit according to the clock signal and the reset signal and receive a portion of the supply current provided by the power supply circuit according to the current load to generate an indication signal for indicating a performance of the power supply circuit.

Abstract: A method of controlling a droplet illumination module/droplet detection module system of an extreme ultraviolet (EUV) radiation source includes irradiating a target droplet with light from a droplet illumination module and detecting light reflected and/or scattered by the target droplet. The method includes determining whether an intensity of the detected light is within an acceptable range. In response to determining that the intensity of the detected light is not within the acceptable range, a parameter of the droplet illumination module is automatically adjusted to set the intensity of the detected light within the acceptable range.

Abstract: Methodology of forming a substantially flat-top illuminating light beam, from a beam at the laser output having a conventionally non-uniform distribution of irradiance, with the use of only a birefringent prismatic element and light-focusing optics. Preferably, the cross-sectional area of such illuminating light distribution is shaped to be elongated or even substantially rectangular to have it used advantageously in various metrological situations such as, for example, the operation of a moving particle analyzer.

Abstract: A board-like connector, a dual-ring bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-ring bridges spaced apart from each other and an insulating layer. Each of the dual-ring bridges includes two carrying rings, two cantilevers respectively extending from and being coplanar with the two carrying rings, two abutting columns respectively extending from the two cantilevers along two opposite directions, and a bridging segment that connects the two carrying rings. The insulating layer connects the two carrying rings of the dual-ring bridges, and the two abutting columns of the dual-ring bridges respectively protrude from two opposite sides of the insulating layer. The two abutting columns of each of the dual-ring bridges are configured to be respectively abutted against two boards.

Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.

Abstract: A coating is included on one or more components of a lithography system. The coating reduces surface roughness of the one or more surfaces, increases flatness of the one or more surfaces, and/or increases uniformity of the one or more surfaces. The coating may be formed on the one or more surfaces using one or more of the techniques described herein. The coating is configured to reduce adhesion of target material particles to the one or more surfaces, is configured to resist buildup of target material particles on the one or more surfaces, is configured to provide resistance against oxidation of the one or more surfaces, is configured to resist thermal damage of the one or more surfaces, and/or is configured to enable the lithography system to operate at higher operating temperatures, among other examples.

Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

Abstract: A probe card device and a dual-arm probe are provided. The dual-arm probe has a probe length, and includes a bifurcation end portion and a testing end portion. The dual-arm probe has two broad side surfaces respectively arranged on two opposite sides thereof. The dual-arm probe has a separation slot that is recessed from a bifurcation opening of the bifurcation end portion toward the testing end portion and that penetrates from one of the two broad side surfaces to the other one, so that two branch arms of the dual-arm probe are defined by the separation slot and are spaced apart from each other. The separation slot has a slot length being 50% to 90% of the probe length. In a cross section of the two branch arms, an area of any one of the two branch arms is 90% to 110% of that of the other one.

Abstract: Extreme ultraviolet (EUV) lithography systems are provided. A EUV scanner is configured to perform a lithography exposure process in response to EUV radiation. A light source is configured to provide the EUV radiation to the EUV scanner. A measuring device is configured to measure concentration of debris caused by unstable target droplets in the chamber. A controller is configured to adjust a first gas flow rate and a second gas flow rate in response to the measured concentration of the debris and a control signal from the EUV scanner. A exhaust device is configured to extract the debris out of the chamber according to the first gas flow rate. A gas supply device is configured to provide a gas into the chamber according to the second gas flow rate. The control signal indicates the lithography exposure process is completed.

Abstract: A package structure and method of forming the same are provided. The package structure includes a semiconductor unit, a package component and an underfill layer. The semiconductor structure unit includes a first semiconductor structure and a second semiconductor structure disposed as side by side, and an isolation region laterally between the first semiconductor structure and the second semiconductor structure. The isolation region vertically extends from a top surface to a bottom surface of the semiconductor structure unit. The semiconductor structure unit is disposed on and electrically connected to the package component. The underfill layer is disposed to fill a space between the semiconductor structure unit and the package component.

Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Abstract: A drink container and a lid assembly thereof are provided. The drink container includes a container body and the lid assembly, the lid assembly includes a first lid and a second lid, the first lid is screwed at an opening end of the container body through screw threads, the first lid has a top portion, and the top portion of the first lid has an opening portion. The second lid is disposed above the first lid, the second lid includes a plunger component, and a bottom portion of the plunger can be engaged with the opening portion and sealed with the opening portion. The plunger component is connected to a connection arm, and one side of the connection arm corresponding to the plunger component is pivotally connected to a pivot portion of the first lid. The plunger component has a second accommodating space configured to accommodate a straw.

Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.