Abstract: Systems and methods for assaying a test entity for a property, without measuring the property, are provided. Exemplary test entities include proteins, protein mixtures, and protein fragments. Measurements of first features in a respective subset of an N-dimensional space and of second features in a respective subset of an M-dimensional space, is obtained as training data for each reference in a plurality of reference entities. One or more of the second features is a metric for the target property. A subset of first features, or combinations thereof, is identified using feature selection. A model is trained on the subset of first features using the training data. Measurement values for the subset of first features for the test entity are applied to thereby obtaining a model value that is compared to model values obtained using measured values of the subset of first features from reference entities exhibiting the property.

Abstract: A lens module for capturing an object light-beam from an object-side is provided. The lens module includes a first lens group, a second lens group, a third lens group, a fourth lens group and a fifth lens group sequentially-arranged from the object-side to an image-side. The five lens groups respectively have at least one lens with positive refractive-power and at least one lens with negative refractive-power. The first, third and fifth lens groups are fixed groups, while the second and fourth lens groups are movable groups. An image apparatus including the lens module is also provided.

Abstract: The present disclosure provides a lithography system comprising a radiation source and an exposure tool including a plurality of exposure columns densely packed in a first direction. Each exposure column includes an exposure area configured to pass the radiation source. The system also includes a wafer carrier configured to secure and move one or more wafers along a second direction that is perpendicular to the first direction, so that the one or more wafers are exposed by the exposure tool to form patterns along the second direction. The one or more wafers are covered with resist layer and aligned in the second direction on the wafer carrier.

Abstract: A method of forming a magnetoresistive (MR) sensor with a composite tunnel barrier comprised primarily of magnesium oxynitride and having a MR ratio of at least 70%, resistance x area (RA) product <1 ohm-?m2, and fewer pinholes than a conventional MgO layer is disclosed. The method involves forming a Mg/MgON/Mg, Mg/MgON/MgN, MgN/MgON/MgN, or MgN/MgON/Mg intermediate tunnel barrier stack and then annealing to drive loosely bound oxygen into adjacent layers thereby forming MgO/MgON/Mg, MgO/MgON/MgON, MgON/MgON/MgON, and MgON/MgON/MgO composite tunnel barriers, respectively, wherein oxygen content in the middle MgON layer is greater than in upper and lower MgON layers. The MgON layer in the intermediate tunnel barrier may be formed by a sputtering process followed by a natural oxidation step and has a thickness greater than the Mg and MgN layers.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize an uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for non-printable dummy features and adding the non-printable dummy features in the IC design layout.

Abstract: The present disclosure provides methods of electron-beam (e-beam) lithography process. The method includes loading a substrate to an electron-beam (e-beam) system such that a first subset of fields defined on the substrate is arrayed on the substrate along a first direction. The method also includes positioning a plurality of e-beam columns having a first subset of e-beam columns arrayed along the first direction. The e-beam columns of the first subset of e-beam columns are directed to different ones of the first subset of fields. The method also includes performing a first exposing process in a scan mode such that the plurality of e-beam columns scans the substrate along the first direction.

Abstract: A heat conducting module includes a main body. The main body includes a first surface and a second surface. The first surface is thermally connected to a heat absorbing body. The second surface is opposite to the first surface and is fluidly connected to a channel. The second surface has a plurality of grooves disposed along a direction. The channel allows a fluid to flow a long the direction. Each of the grooves includes a first sub-groove and at least one second sub-groove. The first sub-groove at least has a third surface close to the first surface. The first sub-groove at least partially communicates with the second sub-groove, and the second sub-groove is at least partially fluidly connected with the third surface.

Abstract: A proportion-integration-derivation (PID) kettle structure includes: a kettle upper cover; a water filling cap, embedded into kettle upper cover; and a PID element, fixed onto inner side of water filling cap, to indicate usage time of a filter core in a kettle. The PID element includes: a guiding axis, disposed at an end inside the water filling cap; a pushing rack, sleeved around the guiding axis; a reset spring, disposed between pushing rack and guiding axis; an arc-shape rack pushing boss, disposed symmetrically on both sides of the pushing rack, used to push the pushing rack to move, when water filling cap is opened or closed; a driving gear, disposed at front end of the pushing rack, to act in cooperation with the pushing rack; and a driven gear, disposed below the driving gear, and connected to rotate along with the driving gear.

Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

Abstract: A TMR sensor that includes a free layer having at least one B-containing (BC) layer made of CoFeB, CoFeBM, CoB, CoBM, or CoBLM, and a plurality of non-B containing (NBC) layers made of CoFe, CoFeM, or CoFeLM is disclosed where L and M are one of Ni, Ta, Ti, W, Zr, Hf, Tb, or Nb. One embodiment is represented by (NBC/BC)n where n?2. A second embodiment is represented by (NBC/BC)n/NBC where n?1. In every embodiment, a NBC layer contacts the tunnel barrier and NBC layers each with a thickness from 2 to 8 Angstroms are formed in alternating fashion with one or more BC layers each 10 to 80 Angstroms thick. Total free layer thickness is <100 Angstroms. The free layer configuration described herein enables a significant noise reduction (SNR enhancement) while realizing a high TMR ratio, low magnetostriction, low RA, and low Hc values.

Abstract: A zoom lens arranged along an optical axis includes a first lens group and a second lens group. The second lens group has at least one aspheric lens. The first lens group moves toward an image side and the second lens group moves away from the image side along the optical axis during zooming. The first lens group is moved for focusing, and the second lens group is moved for zooming.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: A partial decoding circuit with inverse second transform has a transpose buffer, a first-direction inverse residual transform circuit, and a second-direction inverse residual transform circuit. The transpose buffer stores an intermediate inverse residual transform result. The first-direction inverse residual transform circuit processes an inverse quantization output to generate the intermediate inverse residual transform result to the transpose buffer. The second-direction inverse residual transform circuit accesses the transpose buffer to retrieve the intermediate inverse residual transform result, and processes the intermediate inverse residual transform result to generate a final inverse residual transform result, where the final inverse residual transform result of the inverse second transform is further processed by an inverse transform circuit.

Abstract: Aspects of the subject matter described herein relate to file system technology. In aspects, a mechanism is described that allows a file system to handle corrupted file system metadata in a way that provides high availability. When corrupted metadata is detected, the corrupted metadata may be deleted while the file system remains online and available to service file input/output operations that involve non-corrupted metadata.

Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

Abstract: An method including forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion including a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material, forming a through-substrate via through the BEOL wiring portion and the semiconductor base portion, forming an electronic fuse in the BEOL wiring portion adjacent to the through-substrate via, and forming a guard ring in the BEOL wiring portion surrounding the through-substrate via and the electronic fuse in the BEOL wiring portion, the through-substrate via in the semiconductor base portion being free from the guard ring.

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.