Patents by Inventor Ji-Yong Park

Ji-Yong Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220013476
    Abstract: Disclosed is a semiconductor package including a base film that has a first surface and a second surface opposite to the first surface, a plurality of input/output lines on the first surface of the base film, a semiconductor chip disposed on the first surface of the base film and connected to the input/output lines and including a central portion and end portions on opposite sides of the central portion, and a heat radiation pattern on the second surface of the base film The heat radiation pattern corresponds to the semiconductor chip and has a plurality of openings that correspond to the end portions of the semiconductor chip and that vertically overlap the end portions of the semiconductor chip.
    Type: Application
    Filed: February 22, 2021
    Publication date: January 13, 2022
    Inventors: JI-YONG PARK, DUCKGYU KIM
  • Patent number: 11217534
    Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Ji Yong Park, Kyu Oh Lee
  • Publication number: 20210398941
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Application
    Filed: September 3, 2021
    Publication date: December 23, 2021
    Inventors: Rahul JAIN, Ji Yong PARK, Kyu Oh LEE
  • Patent number: 11142922
    Abstract: The present invention relates to a design structure of an apartment house in which a plurality of apartment units, each of which is a maisonette in which two floors including an upper floor and a lower floor are combined into a single apartment unit, are repeatedly arranged in vertical and horizontal directions, wherein, in the design structure, each apartment unit has a living room disposed on the upper floor and a plurality of bedrooms disposed on the lower floor, double pillars spaced apart from each other are installed on side boundaries of adjacent apartment units, the double pillars include a pair of first pillars disposed inside an apartment unit and a pair of second pillars disposed outside the apartment unit and disposed inside another apartment unit adjacent thereto, a first beam member, which serves as a structure carrying a load, is connected to and installed at the first pillar, a second beam member, which serves as a structure carrying a load, is connected to and installed at the second pillar,
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 12, 2021
    Inventors: Dae Yeung Park, Ji Yong Park
  • Patent number: 11139264
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
  • Publication number: 20210307172
    Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.
    Type: Application
    Filed: September 2, 2016
    Publication date: September 30, 2021
    Applicant: INTEL CORPORATION
    Inventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
  • Publication number: 20210271442
    Abstract: A display device includes a signal receiver configured to receive an image signal; a display including a plurality of modules each including a plurality of light sources, and display an image based on the received image signal; and a controller configured to perform first uniformity calibration between light sources within each individual module with regard to the modules, and second uniformity calibration between the modules, wherein the controller controls the first uniformity calibration to be applied to the image signal received in the signal receiver based on a first coefficient determined for each of the light sources within each individual module, controls the second uniformity calibration to be applied to the image signal subjected to the first uniformity calibration based on a second coefficient determined for each of the modules, and controls a calibrated image to be displayed based on the image signal subjected to the second uniformity calibration.
    Type: Application
    Filed: May 14, 2021
    Publication date: September 2, 2021
    Inventors: Ji-yong PARK, Min-jung KIM, Sang-kyun IM, Young-hoon CHO
  • Publication number: 20210190759
    Abstract: The present invention relates to a composition for detecting hydrogen sulfide or measuring a concentration of hydrogen sulfide, and a composition comprising same as an effective ingredient for diagnosing or imaging in vivo inflammation, tissues having hypoxic damage, or cancer.
    Type: Application
    Filed: September 11, 2019
    Publication date: June 24, 2021
    Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jae Min Jeong, Young Ju Kim, Yun-Sang Lee, Ji Yong Park
  • Patent number: 11036457
    Abstract: A display device includes a signal receiver configured to receive an image signal; a display including a plurality of modules each including a plurality of light sources, and display an image based on the received image signal; and a controller configured to perform first uniformity calibration between light sources within each individual module with regard to the modules, and second uniformity calibration between the modules, wherein the controller controls the first uniformity calibration to be applied to the image signal received in the signal receiver based on a first coefficient determined for each of the light sources within each individual module, controls the second uniformity calibration to be applied to the image signal subjected to the first uniformity calibration based on a second coefficient determined for each of the modules, and controls a calibrated image to be displayed based on the image signal subjected to the second uniformity calibration.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-yong Park, Min-jung Kim, Sang-kyun Im, Young-hoon Cho
  • Patent number: 11029912
    Abstract: Provided a display apparatus including a display including a plurality of display modules, each display module of the plurality of display modules including a pixel driving circuit and at least one pixel including a red inorganic light emitting element, a green inorganic light emitting element, and a blue inorganic light emitting element, a signal receiver configured to receive an image signal having a plurality of grayscales, and a controller configured to divide the display into a plurality of regions, each region of the plurality of regions having a same area and including at least one display module among the plurality of display modules, calibrate the image signal to output uniform light from each of the plurality of regions, and control the pixel driving circuit to display an image based on the calibrated image signal.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Yong Park, Young-Hoon Cho, Sang Kyun Im
  • Patent number: 11031360
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Patent number: 11011552
    Abstract: Display substrates and display devices with reduced electrical resistance are disclosed. One inventive aspect includes a switching device, a first wiring and a second wiring. The switching device includes a first semiconductor layer, first and second gate insulation layers, a source electrode and a drain electrode. The source and drain electrodes are formed to electrically connect, through the first and second gate insulation layers, to the first semiconductor layer. The second wiring is formed on the second gate insulation layer and electrically connected to the first wiring.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji-Yong Park, Tae-Gon Kim
  • Publication number: 20210104452
    Abstract: Disclosed are film packages and methods of fabricating package modules. The film package includes a film substrate that includes a chip region and a peripheral region facing each other in a first direction, a plurality of output pads that are arranged in the first direction on the chip region and on the peripheral region, and a semiconductor chip on the chip region and electrically connected to the output pads. The output pads on the chip region are arranged at regular first intervals along the first direction. The output pads include a plurality of first output pads that are arranged at a first pitch along the first direction on the chip region and a plurality of second output pads on the peripheral region. The second output pads are arranged at a second pitch greater than the first pitch of the first output pads.
    Type: Application
    Filed: May 12, 2020
    Publication date: April 8, 2021
    Inventors: SHLE-GE LEE, YOUNGBAE KIM, JI-YONG PARK
  • Patent number: 10971492
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Patent number: 10931573
    Abstract: A Layer 2 network switch is partitionable into a plurality of switch fabrics. The single-chassis switch is partitionable into a plurality of logical switches, each associated with one of the virtual fabrics. The logical switches behave as complete and self-contained switches. A logical switch fabric can span multiple single-chassis switch chassis. Logical switches are connected by inter-switch links that can be either dedicated single-chassis links or logical links. An extended inter-switch link can be used to transport traffic for one or more logical inter-switch links. Physical ports of the chassis are assigned to logical switches and are managed by the logical switch. Legacy switches that are not partitionable into logical switches can serve as transit switches between two logical switches.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: February 23, 2021
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Sathish Kumar Gnanasekaran, Badrinath Kollu, Richard L. Hammons, Ramkumar Vadivelu, Dan Norbert Retter, Jianqiang Zhou, Ponpandiaraj Rajarathinam, Daniel Ji Yong Park Chung
  • Publication number: 20210039480
    Abstract: A photocatalyst device including: a body; a light source part fixed to the body to irradiate ultraviolet light and having an LED and a substrate for fixing the LED thereto; a catalyst part fixed to the body to conduct photocatalytic reaction with the light irradiated by the light source part and thus to generate superoxygen radicals; and a heat radiating part disposed on the light source part to radiate the heat generated from the light source part, whereby the photocatalyst device purifies air and sterilizes and deodorizes the evaporator, while being easily mountable as a single module.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Jae-Ho KIM, Ji-Yong PARK, Youn-Woo LIM, Yong-Jun JEE, Gi-Woo RO, Jun-Seong AHN
  • Publication number: 20210017491
    Abstract: Provided is a method of inducing oligodendrocyte precursor cells (OPCs) through direct reprogramming from human somatic cells into which a nucleic acid molecule encoding an Oct4 protein or Oct4 protein-treated human somatic cells. The method of inducing OPCs by treating Oct4-overexpressing human somatic cells with a low molecular weight substance may establish OPCs with high efficiency in a short period of time through direct reprogramming without via neural stem cells, and thus the OPCs are useful as a cell therapeutic agent for an intractable demyelinating disease.
    Type: Application
    Filed: August 13, 2020
    Publication date: January 21, 2021
    Applicant: Stemlab Inc.
    Inventors: Seung Kwon YOU, Won-Jin YUN, Min Ji PARK, Ji-Yong PARK
  • Publication number: 20210010285
    Abstract: The present invention relates to a design structure of an apartment house in which a plurality of apartment units, each of which is a maisonette in which two floors including an upper floor and a lower floor are combined into a single apartment unit, are repeatedly arranged in vertical and horizontal directions, wherein, in the design structure, each apartment unit has a living room disposed on the upper floor and a plurality of bedrooms disposed on the lower floor, double pillars spaced apart from each other are installed on side boundaries of adjacent apartment units, the double pillars include a pair of first pillars disposed inside an apartment unit and a pair of second pillars disposed outside the apartment unit and disposed inside another apartment unit adjacent thereto, a first beam member, which serves as a structure carrying a load, is connected to and installed at the first pillar, a second beam member, which serves as a structure carrying a load, is connected to and installed at the second pillar,
    Type: Application
    Filed: April 2, 2019
    Publication date: January 14, 2021
    Inventors: DAE YEUNG PARK, JI YONG PARK
  • Patent number: 10867948
    Abstract: A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-woo Kim, Woon-bae Kim, Bo-in Noh, Go-woon Seong, Ji-yong Park
  • Patent number: 10857857
    Abstract: A photocatalyst device including: a body; a light source part fixed to the body to irradiate ultraviolet light and having an LED and a substrate for fixing the LED thereto; a catalyst part fixed to the body to conduct photocatalytic reaction with the light irradiated by the light source part and thus to generate superoxygen radicals; and a heat radiating part disposed on the light source part to radiate the heat generated from the light source part, whereby the photocatalyst device purifies air and sterilizes and deodorizes the evaporator, while being easily mountable as a single module.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: December 8, 2020
    Assignee: HANON SYSTEMS
    Inventors: Jae-Ho Kim, Ji-Yong Park, Youn-Woo Lim, Yong-Jun Jee, Gi-Woo Ro, Jun-Seong Ahn