Patents by Inventor Min Lin

Min Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160050753
    Abstract: A method for fabricating an interposer is provided, which includes the steps of: providing a substrate body having opposite first and second sides and a plurality of conductive through holes communicating the first and second sides; forming an insulating layer on the first side of the substrate body, wherein the insulating layer has a plurality of openings correspondingly exposing the conductive through holes; and forming a plurality of conductive pads in the openings of the insulating layer, wherein the conductive pads are electrically connected to the corresponding conductive through holes, thereby dispensing with the conventional wet etching process and hence preventing an undercut structure from being formed under the conductive pads.
    Type: Application
    Filed: June 15, 2015
    Publication date: February 18, 2016
    Inventors: Wen-Ching Chan, Chien-Min Lin, Po-Yi Wu, Chun-Hung Lu
  • Publication number: 20160039663
    Abstract: A method includes forming a bump on a lower surface of an interposer. A first insulation layer is formed to cover the lower surface and bump. A trench is formed extending from the lower towards an upper surface of the interposer. A polymer supporting adhesive layer is formed to surround the bump and couples between the interposer and a semiconductor chip. The semiconductor chip has at least a sensing component and a conductive pad electrically connected to the sensing component, and the bump is connected to the conductive pad. A via is formed extending from the upper towards the lower surface. A second insulation layer is formed to cover the upper surface and the via. A redistribution layer is formed on the second insulation layer and in the via. A packaging layer is formed to cover the redistribution layer and has a second opening.
    Type: Application
    Filed: August 5, 2015
    Publication date: February 11, 2016
    Inventor: Chien-Min LIN
  • Publication number: 20160039662
    Abstract: A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.
    Type: Application
    Filed: June 23, 2015
    Publication date: February 11, 2016
    Inventors: Chien-Min LIN, Yu-Ting HUANG, Chen-Ning FU, Yen-Shih HO
  • Patent number: 9258883
    Abstract: A via structure includes a ground conductor, a floated conductor and a signal conductor. The ground conductor is electrically coupled to a reference potential. The floated conductor is electrically insulated from the ground conductor. The signal conductor is located between and insulated from the ground conductor and the floated conductor.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: February 9, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Hsien Wu, Min-Lin Lee
  • Patent number: 9249459
    Abstract: The present invention provides methods for analysis of genomic DNA and/or RNA from small samples or even single cells. Methods for analyzing genomic DNA can entail whole genome amplification (WGA), followed by preamplification and amplification of selected target nucleic acids. Methods for analyzing RNA can entail reverse transcription of the desired RNA, followed by preamplification and amplification of selected target nucleic acids.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: February 2, 2016
    Assignee: Fluidigm Corporation
    Inventors: Amy Hamilton, Min Lin, Alain Mir, Martin Pieprzyk
  • Publication number: 20160029022
    Abstract: A video processing apparatus includes a first processing circuit, a second processing circuit, and a control circuit. The first processing circuit performs a first processing operation. The second processing circuit performs a second processing operation different from the first processing operation. The control circuit generates at least one output coding unit to the second processing circuit according to an input coding unit generated from the first processing circuit, wherein the control circuit checks a size of the input coding unit to selectively split the input coding unit into a plurality of output coding units.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 28, 2016
    Inventors: Chia-Yun Cheng, Chih-Ming Wang, Yung-Chang Chang, Chun-Chia Chen, Meng-Jye Hu, Huei-Min Lin
  • Patent number: 9246068
    Abstract: The present disclosure involves a method. The method includes providing a substrate having a layer disposed thereon. A plurality of light-emitting devices is attached to the layer. A gel is applied over the substrate. The gel covers the plurality of light-emitting devices. The gel is shaped into a plurality of lenses. The lenses each cover a respective one of the light-emitting devices. The light-emitting devices are separated from one another. The substrate and the layer are removed.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: January 26, 2016
    Assignee: TSMC SOLID STATE LIGHTING LTD.
    Inventors: Chi-Xiang Tseng, Hsiao-Wen Lee, Min-Sheng Wu, Tien-Min Lin
  • Publication number: 20160020139
    Abstract: A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×1022 atoms/cm3 is formed.
    Type: Application
    Filed: September 5, 2014
    Publication date: January 21, 2016
    Inventors: Wen-Yi Teng, Yuh-Min Lin, Chih-Chien Liu, Chieh-Wen Lo
  • Publication number: 20160019181
    Abstract: A motherboard an electronic device using the same are provided. The motherboard includes a motherboard and a control chip. The processor is adapted to be inserted to a processor base including a plurality of pins. The pins is divided to defined pins and undefined pins. The processor base includes a plurality of electrical contacts. A first part of the electrical contacts are corresponding to the defined pins, and a second part of the electrical contacts are corresponding to the undefined pins. The control chip determines whether to make the motherboard enter an overclocking operation mode according to a control command. When the motherboard is set to be at the overclocking operation mode, the control chip transmits a control signal to the undefined pins of the processor via the second part of the electrical contacts, and then the processor improves operating efficiency.
    Type: Application
    Filed: July 21, 2015
    Publication date: January 21, 2016
    Inventors: Ji-Kuang Tan, Yu-Chen Lee, Bing-Min Lin, Ming-Hung Chung
  • Patent number: 9240503
    Abstract: A photodiode structure includes a photodiode and a concave reflector disposed below the photodiode. The concave reflector is arranged to reflect incident light from above back toward the photodiode.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: January 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Min Lin, Volume Chien, Chih-Kang Chao, Chi-Cherng Jeng, Pin Chia Su, Chih-Mu Huang
  • Patent number: 9235534
    Abstract: A data protecting method for protecting a sub-directory and at least one pre-stored file in a rewritable non-volatile memory module is provided. The method includes receiving a write command from a host system and determining whether a write address indicated by the write command is an address storing a file description block of the sub-directory. The method also includes, when the write address is the address storing a file description block of the sub-directory, determining whether a portion of data streams corresponding to the write command is the same as a corresponding content recorded in the file description block of the sub-directory. The method further includes, when the portion of data streams corresponding to the write command is not the same as the corresponding content recorded in the file description block of the sub-directory, transmitting a write failure signal to the host system.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: January 12, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chin-Min Lin
  • Patent number: 9237631
    Abstract: A light emitting chip operating under a DC power supply is provided. The light emitting chip includes a substrate and a plurality of light emitting elements. The light emitting elements are arranged on the substrate, and have the same or different area sizes. The light emitting elements are driven by a single driving voltage or sectionally driven by a plurality of driving voltages.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: January 12, 2016
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Yu-Sheng Chen, Cheng-Chun Liao, Chia-Yen Lee, Yu-Min Lin
  • Patent number: 9232598
    Abstract: An operating circuit applied to a backlight includes at least one current control circuit, where the current control circuit includes a transistor, an operational amplifier and a switch module. The transistor has a gate, a first electrode and a second electrode, where the first electrode is coupled to a lighting element, and the second electrode is coupled to a resistor. The operational amplifier has positive and negative input terminals, and positive and negative output terminals. The switch module switches a connection relationship between the positive input terminal, the negative input terminal, the reference voltage and the second electrode of the transistor, and switches a connection relationship between the positive output terminal, the negative output terminal and the gate of the transistor to make the close loop form a negative feedback, and the current of the lighting element not influenced by an offset voltage of the operational amplifier.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: January 5, 2016
    Assignee: Realtek Semiconductor Corp.
    Inventors: Shu-Min Lin, Jyi-Si Lo, Ying-Hsi Lin
  • Publication number: 20150380315
    Abstract: A method includes forming a first mask over a substrate through a double patterning process, wherein the first mask comprises a horizontal portion and a plurality of vertical portions protruding over the horizontal portion, and wherein the vertical portions are spaced apart from each other, applying a first etching process to the first mask until a top surface of a portion of the substrate is exposed, applying a second etching process to the substrate to form intra-device openings and inter-device openings, wherein the inter-device openings are formed at the exposed portion of the substrate, filling the inter-device openings and the intra-device openings to form inter-device insulation regions and intra-device insulation regions and etching back the inter-device insulation regions and the intra-device insulation regions to form a plurality of fins protruding over top surfaces of the inter-device insulation regions and the intra-device insulation regions.
    Type: Application
    Filed: September 5, 2015
    Publication date: December 31, 2015
    Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
  • Patent number: 9221039
    Abstract: Disclosed herein are a catalyst, a preparation process thereof, and a process of epoxidizing olefin using the catalyst. The catalyst contains a binder and a titanium silicate as specified. The catalyst disclosed herein has high strength, and shows high catalytic activity in the epoxidation of olefins.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: December 29, 2015
    Assignees: China Petroleum & Chemical Corporation, Hunan Changling Petrochemical Science and Technology Development Co., Ltd., Research Institute of Petroleum Processing, Sinopec
    Inventors: Min Lin, Hua Li, Wei Wang, Chijian He, Xiaoju Wu, Jizao Gao, Xichun She, Jun Long, Qingling Chen
  • Patent number: 9214610
    Abstract: A lighting apparatus includes a first doped semiconductor layer, a light-emitting layer disposed over the first doped semiconductor layer, a second doped semiconductor layer disposed over the light-emitting layer, a first conductive terminal, a second conductive terminal, and a photo-conversion layer. The second doped semiconductor layer has a different type of conductivity than the first doped semiconductor layer. The first conductive terminal and the second conductive terminal each are disposed below the first doped semiconductor layer. The photo-conversion layer is disposed over the second doped semiconductor layer and on side surfaces of the first and second doped semiconductor layers and the light-emitting layer. A bottommost surface of the photo-conversion layer is located closer to the second doped semiconductor layer than bottom surfaces of the first and second conductive terminals.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: December 15, 2015
    Assignee: TSMC SOLID STATE LIGHTING LTD.
    Inventors: Chi-Xiang Tseng, Hsiao-Wen Lee, Min-Sheng Wu, Tien-Min Lin
  • Patent number: 9214229
    Abstract: A family of phase change materials GewSbxTeyNz having a crystallization temperature greater than 410° C., wherein a Ge atomic concentration is within a range from 43% to 54%, a Sb atomic concentration is within a range from 6% to 13%, a Te atomic concentration is within a range from 14% to 23%, and a N atomic concentration is within a range of 15% to 27%, is described. A method for programming a memory device including such phase change materials is also described.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: December 15, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Huai-Yu Cheng, Hsiang-Lan Lung, Che-Min Lin
  • Patent number: 9209040
    Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a first cushion layer, a second cushion layer and an insulating filler. The first cushion layer is peripherally enclosed by the semiconductor substrate, the second cushion layer is peripherally enclosed by the first cushion layer, and insulating filler is peripherally enclosed by the second cushion layer. A method for fabricating the semiconductor device is also provided herein.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 8, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Min Lin, Wei-Lun Hong, Ying-Tsung Chen, Liang-Guang Chen
  • Patent number: 9201195
    Abstract: The present disclosure provides an integrated circuit device comprising a substrate having a back surface and a sensing region disposed in the substrate and being operable to sense radiation projected towards the back surface of the substrate. The device further includes a waveguide disposed over the back surface of the substrate. The waveguide is aligned with the sensing region such that the waveguide is operable to transmit the radiation towards the aligned sensing region. The waveguide includes a waveguide wall, and an inner region disposed adjacent to the waveguide wall. A diffractive index of the waveguide wall is less than a diffractive index of the inner region.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Allen Tseng, Che-Min Lin, Zen-Fong Huang, Volume Chien, Chi-Cherng Jeng
  • Publication number: 20150328183
    Abstract: A pharmaceutical composition for inhibiting tumor metastasis is disclosed. The pharmaceutical composition includes a therapeutically effective amount of 7,7?-Dimethoxyagastisflavone (DMGF) and a pharmaceutically acceptable carrier. The present invention also discloses a use of DMGF for manufacturing a pharmaceutical composition applied to inhibit tumor metastasis. The application of the pharmaceutical composition and the use of the present invention are advantageous for inhibiting tumor metastasis efficiently.
    Type: Application
    Filed: May 15, 2015
    Publication date: November 19, 2015
    Inventors: Kuang-Wen LIAO, Ching-Min LIN, Yu-Ling LIN