Patents by Inventor Pei Yu

Pei Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11682729
    Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Chen-Ming Lee, Kuo-Yi Chao, Mei-Yun Wang, Pei-Yu Chou, Kuo-Ju Chen
  • Patent number: 11676819
    Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11675731
    Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 13, 2023
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
  • Publication number: 20230170397
    Abstract: A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 1, 2023
    Inventors: Chia-Ming HSU, Pei-Yu CHOU, Chih-Pin TSAO, Kuang-Yuan HSU, Jyh-Huei CHEN
  • Patent number: 11664451
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Chieh Yang, Li-Yang Chuang, Pei-Yu Wang, Wei Ju Lee, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11652106
    Abstract: A semiconductor device includes a plurality of semiconductor fins, at least one gate stack, a refill isolation, and an air gap. Each of the semiconductor fins extends in an X direction. Two adjacent ones of the semiconductor fins are spaced apart from each other in a Y direction transverse to the X direction. The at least one gate stack has two stack sections spaced apart from each other in the Y direction. The stack sections are disposed over two adjacent ones of the semiconductor fins, respectively. The refill isolation and the air gap are disposed between the stack sections.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Yu Chou, Yi-Ting Fu, Ting-Gang Chen, Tze-Liang Lee
  • Patent number: 11652043
    Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Yu-Xuan Huang
  • Patent number: 11638667
    Abstract: A transmission device of a hospital bed, the hospital bed includes a body, a head, and a bed end. The transmission device contains: a main motor, a connection rod unit, and a driver. The main motor is disposed on a bottom of the body and includes a socket. The connection rod unit includes a first fixing rod connected to the head and a second fixing rod connected to the bed end. The driver is mounted on the main motor and includes an accommodation space, a driving motor, a reducer, a power cable, and a drive shaft. The first case has a first coupling orifice, and the second case has a second coupling orifice. The power cable is connected between the socket and the driving motor so as to supply a power to the driving motor and to lift or descend the head and the bed end synchronously.
    Type: Grant
    Filed: December 20, 2020
    Date of Patent: May 2, 2023
    Assignee: NANTONG SHUNLONG PHYSICAL THERAPY EQUIPMENT CO.
    Inventor: Pei-Yu Hsu
  • Publication number: 20230125621
    Abstract: A computer-implemented method, system and computer program product for generating visualizations for semi-structured data. Visualization data is extracted from infographics depicting semi-structured data. The visualization data that is extracted includes the traits or characteristics of the semi-structured data depicted in the infographics (e.g., dimension), the characteristics of the infographics (e.g., location of the depicted data), and the constraints or display requirements (e.g., display target value in a particular axis). A trait and constraint rule set is then generated based on the extracted visualization data. The trait and constraint rule set includes a set of rules that maps the display requirements to the particular set of traits or characteristics exhibited by the semi-structured data displayed in the infographics.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Inventors: Wen Pei Yu, Ji Hui Yang, Xiao Ming Ma, Rui Wang, Jing James Xu
  • Publication number: 20230119302
    Abstract: An auxiliary vehicle mirror device includes a main rod unit, a securing unit and an auxiliary mirror unit. The main rod unit includes a connecting rod, first and second fixture rods connected perpendicularly to opposite ends of the connecting rod and extending respectively in opposite directions, and first and second ball fixtures disposed respectively on the first and second fixture rods. The first ball fixture is engaged with a first socket seat of the securing unit to be freely rotatable relative to it. The second ball fixture is engaged with a second socket seat of the auxiliary mirror unit to be freely rotatable relative to it.
    Type: Application
    Filed: March 18, 2022
    Publication date: April 20, 2023
    Applicant: KEN SEAN INDUSTRIES CO., LTD.
    Inventors: Peng-Kai CHUANG, Pei-Yu HSIEH
  • Publication number: 20230124311
    Abstract: An ultrasonic device is provided for use on a biological tissue, and includes a base assembly on which a vibrator is mounted, and an ultrasonic probe. The base assembly includes an annular base having at least two pairs of abutment protrusions for abutting against the biological tissue, and an installation base coaxially disposed on and rotatable relative to the annular base between two test positions. The installation base has a through hold in which the ultrasonic probe is inserted.
    Type: Application
    Filed: December 8, 2021
    Publication date: April 20, 2023
    Inventors: Chih-Chung HUANG, Pei-Yu CHEN
  • Patent number: 11632364
    Abstract: A controller may be used to create and process an assertion, in some cases, to implement single-sign on (SSO) in a computer network. In some examples, the controller includes processing circuitry coupled to a storage device. The processing circuitry is configured to create the assertion, where the assertion includes information indicative of a set of attributes and parse the assertion to determine the set of attributes. Additionally, the processing circuitry is configured to determine if each attribute of the set of attributes maps to a plurality of primary user groups stored in the storage device. Based on determining that an attribute of the set of attributes does not map to at least one primary user group of the plurality of primary user groups, the processing circuitry is configured to create a set of secondary user groups and a set of secondary user group names corresponding to the attribute.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: April 18, 2023
    Assignee: Juniper Networks, Inc.
    Inventors: Gurminder Singh, Pei-Yu Yang, Mamata Devabhaktuni
  • Patent number: 11623371
    Abstract: A UV (ultraviolet) curing apparatus for a contact-lens polymerization process is provided. A UV curing module is equipped for the mold cavities of contact-lens curing molds, including a plurality of first UV light sources arranged above the mold cavities and a plurality of second UV light sources arranged below the mold cavities. A plurality of light output areas of a first light guide device guides the light beams emitted by the first UV light sources to illuminate upper light receiving surfaces of the molds. A plurality of reflecting plates of a second light guide device reflects and scatters the light beams emitted by the second UV light sources to lower light receiving surfaces of the molds. Thereby, the contact-lens polymer inside the molds is uniformly cured, and the yield is raised.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: April 11, 2023
    Assignee: Hope Vision Co., Ltd.
    Inventors: Shih Hong Chu, Zheng Jun Su, Cheng Tai Jao, Hsin Pei Yu, Huan Chiu Tsen
  • Patent number: 11616143
    Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Huan-Chieh Su, Pei-Yu Wang, Chih-Hao Wang
  • Publication number: 20230079770
    Abstract: In some examples, a system includes a network managed by a service provider and configured to provide access to one or more objects to a set of tenants each having one or more users, the service provider and the set of tenants being part of a set of entities that form a hierarchy, and a controller having access to the network. The controller is configured to obtain data indicative of a set of parameters, where the data indicative of the set of parameters is associated with an owner entity of the set of entities, generate a rule which incorporates the set of parameters, where the rule enables the controller to control access to an object of the one or more objects, and add the rule to a rules database, wherein the rules database is accessible to the controller.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 16, 2023
    Inventors: Gurminder Singh, Pei-Yu Yang, Rong Xie
  • Publication number: 20230061080
    Abstract: This disclosure is directed to devices, systems, and techniques for enforcing access to resources within a computer network. In some examples, a system includes a network managed by a service provider and configured to provide a plurality of microservices to a plurality of tenants each having one or more users and a controller having access to the network. The controller is configured to output, to a user interface, data indicative of a plurality of capabilities for presentation by the user interface and receive, from the user interface, data indicative of a user selection of a set of capabilities and a user selection of a new role identifier. The controller is further configured to create, based on the set of capabilities and the role identifier, a role which enables access to a set of actions within a computer network, the set of actions corresponding to the set of capabilities.
    Type: Application
    Filed: October 19, 2022
    Publication date: March 2, 2023
    Inventors: Gurminder Singh, Pei-Yu Yang, Rong Xie
  • Patent number: 11594612
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11581437
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Pei-Yu Wang, Cheng-Ting Chung, Chih-Hao Wang
  • Patent number: 11581410
    Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain (LDD) region, the first LDD region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source/drain region; a source/drain contact extending through the ILD layer, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Pei-Yu Wang, Chi On Chui
  • Publication number: 20230043635
    Abstract: A method includes forming a gate structure over a substrate; forming a source/drain region adjacent the gate structure; forming a first interlayer dielectric (ILD) over the source/drain region; forming a contact plug extending through the first ILD that electrically contacts the source/drain region; forming a silicide layer on the contact plug; forming a second ILD extending over the first ILD and the silicide layer; etching an opening extending through the second ILD and the silicide layer to expose the contact plug, wherein the silicide layer is used as an etch stop during the etching of the opening; and forming a conductive feature in the opening that electrically contacts the contact plug.
    Type: Application
    Filed: March 14, 2022
    Publication date: February 9, 2023
    Inventors: Pei-Yu Chou, Chia-Ming Hsu, Tze-Liang Lee