Abstract: An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Abstract: A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.

Abstract: Embodiments of the present disclosure relate to a method, system, and computer program product for predictive models. According to the method, a processor may provide a first list including at least one input variable of a predictive model and a second list including a plurality of variables of the predictive model. For each of input variables in the second list, the processor may determine contribution of the input variable to prediction of the predictive model with respect to the at least one input variable in the first list. The processor may update the first list by moving an input variable in the second list into the first list based on the determined contribution of the plurality of input variables. The processor may render one or more of input variables in the updated first list based on an order of the input variables in the updated first list.

Abstract: A method for manufacturing a semiconductor structure includes: forming a semiconductor device on a main region of the device substrate, the device substrate having a peripheral region surrounding the main region; forming a first filling layer on the peripheral region of the device substrate; forming a second filling layer over the first filling layer and the semiconductor device after forming the first filling layer, the second filling layer having a polishing rate different from that of the first filling layer; performing a planarization process over the second filling layer to remove a portion of the second filling layer so that a remaining portion of the second filling layer has a planarized surface opposite to the device substrate; and bonding the device substrate to a carrier substrate through the first filling layer and the remaining portion of the second filling layer.

Abstract: A head-mounted display device assembly and an external adjustment module are provided. The head-mounted display device assembly includes a head-mounted display device and the external adjustment module. The head-mounted display device has a first lens and a second lens corresponding to both eyes, and also has a driven mechanism. The first lens and the second lens are respectively coupled to the driven mechanism. The external adjustment module is used for assembling and electrically connecting to the head-mounted display device, and includes a driving element and a transmission element. In a coupling state, the transmission element is coupled to the driving element and the driven mechanism, and the driving element drives the driven mechanism via the transmission element to adjust a distance between the first lens and the second lens. In a separation state, at least one of the driving element and the driven mechanism is separated from the transmission element.

Abstract: A semiconductor device and method of manufacture which utilize isolation structures between semiconductor regions is provided. In embodiments different isolation structures are formed between different fins in different regions with different spacings. Some of the isolation structures are formed using flowable processes. The use of such isolation structures helps to prevent damage while also allowing for a reduction in spacing between different fins of the devices.

Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A semiconductor device including an embedded channel structure, a sidewall channel structure and a gate electrode structure is provided. The embedded channel structure is disposed on a substrate. The sidewall channel structure is disposed on the substrate, and located at a lateral side of the embedded channel structure. The gate electrode structure is disposed on the substrate, encircles the embedded channel structure and is located between the embedded channel structure and the sidewall channel structure.

Abstract: A pixel package includes a base material, a circuit structure, light-emitting semiconductor elements, a non-light-emitting semiconductor element, and a light-transmitting adhesive layer. The base material has an upper surface, a lower surface, and a side surface. The circuit structure is buried in the base material and includes an first circuit layer exposed from the upper surface, bottom electrodes exposed from the lower surface, and a middle circuit layer between the upper circuit layer and the plurality of bottom electrodes and covered by the base material. The light-emitting semiconductor elements are on the upper surface and electrically connected to the circuit structure. The non-light-emitting semiconductor element is buried in the base material and directly connected to the middle circuit layer, and at least one outside surface is exposed. The light-transmitting adhesive layer covers the light-emitting semiconductor elements and is in direct contact with the base material.

Abstract: A semiconductor device includes a substrate, nanostructures vertically suspended above the substrate, a metal gate structure wrapping each of the nanostructures, an epitaxial feature having a first sidewall in physical contact with end portions of the nanostructures, and an air gap disposed between the epitaxial feature and the metal gate structure. The air gap exposes the first sidewall of the epitaxial feature and the end portions of the nanostructures.

Abstract: Disclosed are a computer-implemented method, a system and a computer program product for model exploration. Model feature importance of each model of a plurality of models can be obtained, the plurality of models can be grouped into a plurality of model clusters based on the model feature importance of each model, and the model feature importance can be presented by box-plot or confidence interval.

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

Abstract: Techniques for automatically manufacturing mechanical parts are described. A first estimate of manufacturing cost for a first mechanical part is generated using a first machine learning model. In response to determining that the first estimate of manufacturing cost for the first mechanical part falls within a range of effectivity for the first machine learning model, a second estimate of manufacturing cost for the first mechanical part is generated using a second machine learning model. An expected cost error in the second estimate of manufacturing cost for the first mechanical part is determined, and upon determining that the expected cost error falls within a pre-determined acceptable range, automatic manufacturing of the first mechanical part is facilitated.

Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

Abstract: An interconnection structure includes a first conductive feature disposed in a dielectric material, a first etch stop layer disposed over the dielectric material, a first dielectric layer disposed over the first etch stop layer, and a second conductive feature extending through the first dielectric layer and the first etch stop layer and in electrical contact with the first conductive feature. The first etch stop layer includes a boron-based layer, and an oxygen-rich boron-containing layer in contact with the boron-based layer.

Abstract: A head-mounted display device assembly and an external adjustment module are provided. The head-mounted display device assembly includes a head-mounted display device and the external adjustment module. The head-mounted display device has a first lens and a second lens corresponding to both eyes, and also has a driven mechanism. The first lens and the second lens are respectively coupled to the driven mechanism. The external adjustment module is used for assembling and electrically connecting to the head-mounted display device, and includes a driving element and a transmission element. In a coupling state, the transmission element is coupled to the driving element and the driven mechanism, and the driving element drives the driven mechanism via the transmission element to adjust a distance between the first lens and the second lens. In a separation state, at least one of the driving element and the driven mechanism is separated from the transmission element.

Abstract: The invention generally relates to methods of removing potassium, rubidium, and/or cesium, selectively or in combination, from brines using tetrafluoroborates. Also disclosed are methods of producing potassium, rubidium, and/or cesium chlorides using ionic liquids and exchange media. This invention also generally relates to treated geothermal brine compositions containing reduced concentrations of silica, iron, and potassium compared to the untreated brines. Exemplary compositions of the treated brine contain a concentration of silica ranging from about 0 mg/kg to about 15 mg/kg, a concentration of iron ranging from about 0 mg/kg to about 10 mg/kg, and a concentration of potassium ranging from about 300 mg/kg to about 8500 mg/kg. Other exemplary compositions of the treated brines also contain reduced concentrations of elements like rubidium, cesium, and lithium.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.