Patents by Inventor Shu Lin

Shu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated Circuit Package and Method
    Publication number: 20210272875
    Abstract: In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Yuan Sheng Chiu, Chih-Kai Cheng, Tsung-Shu Lin
  • Flow metadata exchanges between network and security functions for a security service
    Patent number: 11095612
    Abstract: Techniques for providing flow meta data exchanges between network and security functions for a security service are disclosed. In some embodiments, a system/process/computer program product for providing flow meta data exchanges between network and security functions for a security service includes receiving a flow at a network gateway of a security service from a software-defined wide area network (SD-WAN) device; inspecting the flow to determine meta information associated with the flow; and communicating the meta information associated with the flow to the SD-WAN device.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 17, 2021
    Assignee: Palo Alto Networks, Inc.
    Inventors: Anand Oswal, Arivu Mani Ramasamy, Bhaskar Bhupalam, Shu Lin
  • Package structure having line connected via portions
    Patent number: 11088079
    Abstract: A package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Kai Cheng, Tsung-Shu Lin, Tsung-Yu Chen, Hsien-Pin Hu, Wen-Hsin Wei
  • Semiconductor structure
    Patent number: 11088048
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor includes a substrate, a block bonded on the substrate, a first die bonded on the block, a second die disposed over the first die, and a heat spreader covering the block and having a surface facing toward and proximal to the block. A thermal conductivity of the heat spreader is higher than a thermal conductivity of the block.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hsi Wu, Wensen Hung, Tsung-Shu Lin, Shih-Chang Ku, Tsung-Yu Chen, Hung-Chi Li
  • Semiconductor Device and Method of Manufacture
    Publication number: 20210233833
    Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
  • Package structure and method of manufacturing the same
    Patent number: 11069642
    Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and conductive pads. The redistribution circuit structure is located on and electrically connected to the semiconductor die, the redistribution circuit structure includes a first contact pad having a first width and a second contact pad having a second width. The conductive pads are located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure is located between the conductive pads and the semiconductor die. The first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Hsuan-Ning Shih
  • Package structure and method and equipment for forming the same
    Patent number: 11062971
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Semiconductor device and method for fabricating the same
    Patent number: 11062953
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210193550
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Shu Lin, Tsung-Yu Chen, Chien-Yuan Huang, Chen-Hsiang Lao
  • PERMEABLE SPRAYING DEVICE FOR MAKING DRUG TABLETS
    Publication number: 20210186817
    Abstract: A permeable spraying device for making drug tablets mainly comprises a carrying platform, a spraying equipment, a flattening device and a control equipment, the carrying platform defines a powder dropping area and a flattened spraying area, and a moving device combined with the carrying platform is capable of moving vertically. The spraying equipment is mounted above the carrying platform, and the spraying equipment comprises a powder box, a colloid spraying equipment, a driving device and a placement platform. The placement platform is disposed with a plurality of supplementary colloid carriers. The flattening device is installed on the carrying platform and moves horizontally back and forth in the flattened spraying area. The control equipment is equipped with a storage unit and an execution control unit. A multi-layer drug body structure can be formed by deposition, stacking and bonding.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 24, 2021
    Inventors: Kuo-Ming HUANG, Yen-Shu LIN, Yen-Chao YANG, Yao-Jen LIANG
  • Error correction using cyclic code-based LDPC codes
    Patent number: 11038530
    Abstract: Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT).
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: June 15, 2021
    Assignee: WESTHOLD CORPORATION
    Inventors: Shu Lin, Khaled Ahmed Sabry Abdel-Ghaffar, Juane Li, Keke Liu
  • Contact Pad for Semiconductor Device
    Publication number: 20210175191
    Abstract: A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: Chang-Chia Huang, Tsung-Shu Lin, Cheng-Chieh Hsieh, Wei-Cheng Wu
  • Routing design of dummy metal cap and redistribution line
    Patent number: 11031352
    Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Meng-Tsan Lee, Tsung-Shu Lin, Wei-Cheng Wu, Chien-Chia Chiu, Chin-Te Wang
  • Data decoding method using LDPC code as error correction code and data transmitting method thereof
    Patent number: 11031954
    Abstract: A data transmitting method using an LDPC code as an error correction code is provided. The method includes providing a parity check matrix of LDPC code, wherein the size of the parity check matrix is (m1+m2)×(n1+n2); in a sending side, encoding an input data of K bits with a encoder to generate a first block code of (n1+n2) bits, according to the parity check matrix; through a transmitting channel, sending n1 bits of the first block code from the sending side to a receiving side, wherein n2 bits of the first block code are not transmitted; and receiving the n1 bits of the first block code in the receiving side, and using the parity check matrix to perform a decoding algorithm to the received first block code to iterative decodes a second block code of (n1+n2) bits with a decoder. Furthermore, a data decoding method thereof is also provided.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 8, 2021
    Assignee: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Shu Lin, Yen-Chin Liao
  • Heat spreading device and method
    Patent number: 11018073
    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Shu Lin, Wensen Hung, Hung-Chi Li, Tsung-Yu Chen
  • SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210151580
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Integrated circuit package and method
    Patent number: 11011451
    Abstract: In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan Sheng Chiu, Chih-Kai Cheng, Tsung-Shu Lin
  • Device and Method for UBM/RDL Routing
    Publication number: 20210143131
    Abstract: An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.
    Type: Application
    Filed: January 20, 2021
    Publication date: May 13, 2021
    Inventors: Meng-Tsan Lee, Wei-Cheng Wu, Tsung-Shu Lin
  • MACROCYCLIC COMPOUNDS AS TRK KINASES INHIBITORS
    Publication number: 20210139506
    Abstract: Provided are certain TRK inhibitors, pharmaceutical compositions thereof, and methods of use thereof.
    Type: Application
    Filed: March 27, 2019
    Publication date: May 13, 2021
    Applicants: Fochon Pharmaceuticals, Ltd., Shanghai Fochon Pharmaceutical Co., LTD.
    Inventors: Huajie ZHANG, Qihong LIU, Chengxi HE, Weipeng ZHANG, Rui TAN, Bin LIU, Hong FU, Haohan TAN, Lijun YANG, Hongbin LIU, Yunling WANG, Yuwei GAO, Zongyao ZOU, Yanxin LIU, Shu LIN, Tongshuang LI, Xingdong ZHAO, Weibo WANG
  • Semiconductor device methods of manufacture
    Patent number: 10978373
    Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung