Patents by Inventor Trung (Tim) Trinh

Trung (Tim) Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040121563
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Application
    Filed: November 21, 2003
    Publication date: June 24, 2004
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 6753565
    Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: June 22, 2004
    Assignee: Micron Technology, Inc.
    Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
  • Publication number: 20040113644
    Abstract: Various aspects of the invention provide methods of manufacturing probe cards and test systems which may test microelectronic components using such probe cards. In one specific example, a probe card may be manufactured by forming a plurality of blind holes in a substrate, with each hole having a closed bottom spaced from a back of the substrate by a back thickness. An electrically conductive metal may be deposited on the substrate to fill the holes and define an overburden on the substrate. The metal in each hole may define a conductor. At least a portion of the overburden may be removed to electrically isolate each of the conductors from one another. A portion of the substrate including the back thickness is removed to define an array of pins extending outwardly from a remaining thickness of the substrate, with each pin being an exposed length of one of the conductors.
    Type: Application
    Filed: December 8, 2003
    Publication date: June 17, 2004
    Inventors: Alan G. Wood, Trung T. Doan, David R. Hembree
  • Publication number: 20040113283
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Application
    Filed: November 21, 2003
    Publication date: June 17, 2004
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 6750089
    Abstract: The invention includes a method of forming a conductive interconnect. An electrical node location is defined to be supported by a silicon-containing substrate. A silicide is formed in contact with the electrical node location. The silicide is formed by exposing the substrate to hydrogen, TiCl4 and plasma conditions to cause Ti from the TiCl4 to combine with silicon of the substrate to form TiSix. Conductively doped silicon material is formed over the silicide. The conductively doped silicon material is exposed to one or more temperatures of at least about 800° C. The silicide is also exposed to the temperatures of at least about 800° C.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: June 15, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung Tri Doan, Howard E. Rhodes, Sujit Sharan, Philip J. Ireland, Martin Ceredig Roberts
  • Patent number: 6750069
    Abstract: A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: June 15, 2004
    Assignee: Micron Technology, Inc.
    Inventors: D. Mark Durcan, Trung T. Doan, Roger Lee, Dennis Keller, Ren Earl
  • Patent number: 6750091
    Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: June 15, 2004
    Assignee: Micron Technology
    Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
  • Patent number: 6748619
    Abstract: A hand-held, electric-powered cleaning device used to wash elevated or difficult-to-reach surfaces. The device includes a length adjustable elongated pole with a rotating brush assembly attached at its distal end. Attached to the proximal end of the elongated pole is a handle assembly that includes a battery housing and a hand grip assembly with a brush control switch and a hose connector fitting. Disposed inside the elongated pole is a coiled water conduit that connects to a standard hose fitting located in the end of the handle assembly and terminates in the brush assembly to deliver water to the brush assembly. Also disposed inside the handle assembly is a soap delivery system to deliver soap to the water conduit.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: June 15, 2004
    Inventor: Trung Thieu Quach
  • Patent number: 6746934
    Abstract: An improved atomic layer doping apparatus is disclosed as having multiple doping regions in which individual monolayer species are first deposited and then dopant atoms contained therein are diffused into the substrate. Each doping region is chemically separated from adjacent doping regions. A loading assembly is programmed to follow pre-defined transfer sequences for moving semiconductor substrates into and out of the respective adjacent doping regions. According to the number of doping regions provided, a plurality of substrates could be simultaneously processed and run through the cycle of doping regions until a desired doping profile is obtained.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: June 8, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Trung T. Doan
  • Patent number: 6743724
    Abstract: A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: June 1, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Trung T. Doan, Guy T. Blalock, Mark Durcan, Scott G. Meikle
  • Patent number: 6743699
    Abstract: A plurality of semiconductor dice are provided on a substrate having a first side and a second side, with the semiconductor dice being spaced from one another by scribe line area. A stencil is positioned over at least one of the first side and the second side of the substrate. The stencil has masking sections which cover at least portions of the scribe line area. A polymer is applied through the positioned stencil onto the first or second side of the substrate over which the stencil is received, with the stencil substantially precluding the polymer from being applied on the covered portions of the scribe line area. After the applying, portions of the scribe line area are cut into and the plurality of dice are singulated from the substrate. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: June 1, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Trung Tri Doan
  • Patent number: 6739944
    Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung Tri Doan
  • Patent number: 6740552
    Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
  • Patent number: 6738259
    Abstract: An apparatus is described that is capable of receiving a number of different types of flash memory cards using a single slot. The apparatus includes a housing that defines a slot to receive different types of removable memory cards. The slot includes a central region of a first height and outer regions of a second height. A plurality of electrically conductive contact areas are disposed within the slot. The apparatus may receive, for example, any one of a Smart Media flash memory card, a Memory Stick flash memory card, a Secure Digital flash memory card, and MultiMedia flash memory card.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: May 18, 2004
    Assignee: Imation Corp.
    Inventors: Trung V. Le, Robert W. Tapani
  • Patent number: 6738960
    Abstract: Some embodiments provide a method of producing sub-optimal routes for a net having a set of pins in a region of an integrated-circuit (“IC”) layout. In some embodiments, such a method is used for a router that partitions the region into a plurality of sub-regions. This method initially identifies a first set of sub-regions that contain the net's pins. It then obtains a second set of sub-regions by adding a third set of sub-regions to the first set of sub-regions. Each sub-region in the third set does not contain any pins of the net. For the second set of sub-regions, the method then identifies a first set of routes, where each route traverses the sub-regions in the second set.
    Type: Grant
    Filed: January 5, 2002
    Date of Patent: May 18, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset, Yang-Trung Lin
  • Publication number: 20040089631
    Abstract: In certain implementations, methods and apparatus include an antenna assembly having at least two overlapping and movable surface microwave plasma antennas. The antennas have respective pluralities of microwave transmissive openings formed therethrough. At least some of the openings of the respective antennas overlap with at least some of the openings of another antenna, and form an effective plurality of microwave transmissive openings through the antenna assembly. Microwave energy is passed through the effective plurality of openings of the antenna assembly and to a flowing gas effective to form a surface microwave plasma onto a substrate received within the processing chamber. At least one of the antennas is moved relative to another of the antennas to change at least one of size and shape of the effective plurality of openings through the antenna assembly effective to modify microwave energy passed through the antenna assembly to the substrate.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 13, 2004
    Inventors: Guy T. Blalock, Trung Tri Doan
  • Publication number: 20040092132
    Abstract: A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in composition from the first precursor gas is flowed to the first monolayer within the chamber under surface microwave plasma conditions within the chamber effective to react with the first monolayer and form a second monolayer on the substrate which is different in composition from the first monolayer. The second monolayer includes components of the first monolayer and the second precursor. In one implementation, the first and second precursor flowings are successively repeated effective to form a mass of material on the substrate of the second monolayer composition. Additional and other implementations are contemplated.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 13, 2004
    Inventors: Trung Tri Doan, Guy T. Blalock, Gurtej S. Sandhu
  • Patent number: 6734121
    Abstract: In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: May 11, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Moore, Trung Tri Doan
  • Publication number: 20040088660
    Abstract: Search functions of a physical layout tool are performed by converting a given physical layout name and selected searching layout names from string representations into numerical representations and comparing the converted numerical representation of the given physical layout name with the converted numerical representations of searching physical layout names until a match occurs. In one embodiment, metal and via layer numbers included in string representations of physical layout names are converted to integer values by selecting number characters from predetermined positions in a string, such as number characters that identify the metal or via layer.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Inventor: Trung Tran
  • Publication number: 20040087251
    Abstract: The invention includes a semiconductive processing method of electrochemical-mechanical removing at least some of a conductive material from over a surface of a semiconductor substrate. A cathode is provided at a first location of the wafer, and an anode is provided at a second location of the wafer. The conductive material is polished with the polishing pad polishing surface. The polishing occurs at a region of the conductive material and not at another region. The region where the polishing occurs is defined as a polishing operation location. The polishing operation location is displaced across the surface of the substrate from said second location of the substrate toward said first location of the substrate. The polishing operation location is not displaced from said first location toward said second location when the polishing operation location is between the first and second locations.
    Type: Application
    Filed: June 20, 2003
    Publication date: May 6, 2004
    Inventors: Trung Tri Doan, Scott G. Meikle