Patents by Inventor Trung (Tim) Trinh

Trung (Tim) Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040040863
    Abstract: A method and an apparatus for electrochemically removing a metal from a substrate surface with an electrolyte and an electrode that has a surface defining a shape suitable to cause substantially uniform removal of a metal-containing surface.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Whonchee Lee, Scott Meikle, Trung Doan, Eugene P. Marsh
  • Publication number: 20040043603
    Abstract: A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In addition, the pin contacts are formed by terminal portions of the conductive members. The fabrication method includes the steps of forming the openings and the conductive members, and then thinning and etching the die to form the pin contacts. An alternate embodiment female component includes female conductive members configured to physically and electrically engage pin contacts on a mating component of a stacked assembly.
    Type: Application
    Filed: June 10, 2003
    Publication date: March 4, 2004
    Inventors: Alan G. Wood, Trung Tri Doan
  • Publication number: 20040039774
    Abstract: A plurality of virtual circuits, each including at least two network nodes, may be established over a single network connection for inter-process messaging. The network connection may be opened asynchronously via a non-blocking open. A virtual circuit including three or more nodes may be implemented in a star formation or a relay formation. Messages may be sent as unicast or broadcast messages. An additional virtual circuit may be opened for the purpose of transmitting status information regarding the network connection between the networked computer systems.
    Type: Application
    Filed: August 20, 2002
    Publication date: February 26, 2004
    Inventors: Ming Xu, Phuong Thao Trung Le
  • Publication number: 20040036065
    Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
    Type: Application
    Filed: August 20, 2003
    Publication date: February 26, 2004
    Inventors: Trung T. Doan, D. Mark Durcan, Brent D. Gilgen
  • Publication number: 20040033650
    Abstract: A contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 19, 2004
    Inventors: Gurtej S. Sandhu, Trung T. Doan, Tyler A. Lowrey
  • Patent number: 6693499
    Abstract: A lumped element ring balun (60) including elements patterned on a monolithic substrate (62) in a compact design. The balun (60) includes four inductors (64, 66, 68, 70) and a plurality of capacitors (190, 192, 198, 202, 214, 226) electrically coupled together to provide RF output signals that are 180° out of phase with each other. The inductors (64-70) are symmetrically disposed in a rectangular area on the substrate (62). A first pair of the inductors (64, 66) is positioned at one end of the rectangular area, and a second pair of the inductors (68, 70) is positioned at opposite end of the rectangular area. All of the capacitors are formed on the substrate (62) in a central circuit area (72) between the first pair of inductors (64, 66) and the second pair of inductors (68, 70). Inner ends (76, 92, 98, 106) are coupled to circuit elements in the circuit area (72) by a metallized trace (120, 136, 150, 170) extending through an air bridge (124, 140, 154, 174).
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: February 17, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: William R. Goyette, Karl D. Peterschmidt, Trung H. Lam
  • Patent number: 6693319
    Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: February 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez
  • Patent number: 6689661
    Abstract: A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: February 10, 2004
    Assignee: Micron Technology, Inc.
    Inventors: D. Mark Durcan, Trung T. Doan, Roger Lee, Dennis Keller, Ren Earl
  • Patent number: 6689624
    Abstract: This invention pertains to a method of fabricating a trenchless MRAM structure and to the resultant MRAM structure. The MRAM structure of the invention has a pinned layer formed within protective sidewalls formed over a substrate. The protective sidewalls facilitate formation of the MRAM structure by a self-aligning process.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: February 10, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Trung T. Doan, Roger Lee, Dennis Keller, Gurtej Sandhu, Ren Earl
  • Patent number: 6690044
    Abstract: A multilayer heterostructure is provided a planarization layer superjacent a semiconductor substrate. The planarization layer comprises tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (“BPSG”) or tetraethylorthosilicate (“TEOS”). A barrier film having a structural integrity is superjacent the planarization layer. A second layer is formed superjacent the barrier film. The second layer comprises tungsten, titanium, tantalum, copper, aluminum, borophosphosilicate glass (“BPSG”) or tetraethylorthosilicate (“TEOS”). Heating causes the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: February 10, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Trung T. Doan, Randhir P. S. Thakur, Yauh-Ching Liu
  • Publication number: 20040020511
    Abstract: A method for providing a high flux of point of use activated reactive species for semiconductor processing wherein a workpiece is exposed to a gaseous atmosphere containing a transmission gas that is substantially nonattenuating to preselected wavelengths of electromagnetic radiation. A laminar flow of a gaseous constituent is also provided over a substantially planar surface of the workpiece wherein a beam of the electromagnetic radiation is directed into the gaseous atmosphere such that it converges in the laminar flow to provide maximum beam energy in close proximity to the surface of the workpiece, but spaced a finite distance therefrom. The gaseous constituent is dissociated by the beam producing an activated reactive species that reacts with the surface of the workpiece.
    Type: Application
    Filed: March 20, 2003
    Publication date: February 5, 2004
    Inventors: Gurtej S. Sandhu, Trung T. Doan
  • Patent number: 6683005
    Abstract: The invention includes a method of treating a predominantly inorganic dielectric material on a semiconductor wafer. A laser is utilized to generate activated oxygen species. Such activated oxygen species react with a component of the dielectric material to increase an oxygen content of the dielectric material. The invention also includes a method of forming a capacitor construction. A first capacitor electrode is formed to be supported by a semiconductor substrate. A dielectric material is formed over the first capacitor electrode. A precursor is provided at a location proximate the dielectric material, and a laser beam is focused at such location. The laser beam generates an activated oxygen species from the precursor. The activated oxygen species contacts the dielectric material. Subsequently, a second capacitor electrode is formed over the dielectric material.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: January 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung Tri Doan
  • Patent number: 6682943
    Abstract: A method of forming minimally spaced MRAM structures is disclosed. A photolithography technique is employed to define masking patterns, on the sidewalls of which spacers are subsequently formed to reduce the distance between any of the two adjacent masking patterns. A filler material is next used to fill in the space around the masking patterns and to form filler plugs. The masking patterns and the spacers are removed using the filler plugs as a hard mask. Digit and word lines of MRAM structures are subsequently formed.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: January 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: D. Mark Durcan, Gurtej Sandhu, Trung T. Doan, Roger Lee, Dennis Keller, Ren Earl
  • Patent number: 6666681
    Abstract: Agricultural forced air heaters marketed for use in farm buildings which house poultry, swine, and livestock are quite susceptible to the accumulation of dust and other particles. These heaters are gas fired units having combustion, air mixing, blower and blower motor components assembled in a parallelepiped housing. To admit incoming air for their blowers and burners the heaters have multiple openings in the form of grid-like air intake ports on various heater sides. In the environments in which they are used the extensive use of air intake holes is a disadvantage. In the heater herein panels form four distinct chambers, a blower chamber, an air mixing chamber, a motor chamber, and a combustion chamber. Air inlets open into the motor chamber as the only air inlets in the heater housing. These air inlets provide all of the air for the heater.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: December 23, 2003
    Inventor: Trung Quang Do
  • Patent number: 6663470
    Abstract: A method and apparatus for releasably attaching a planarizing medium, such as a polishing pad, to the platen of a chemical-mechanical planarization machine. In one embodiment, the apparatus can include several apertures in the upper surface of the platen that are coupled to a vacuum source. When a vacuum is drawn through the apertures in the platen, the polishing pad is drawn tightly against the platen and may therefore be less likely to wrinkle when a semiconductor substrate is engaged with the polishing pad during planarization. When the vacuum is released, the polishing pad can be easily separated from the platen. The apparatus can further include a liquid trap to separate liquid from the fluid drawn by the vacuum source through the apertures, and can also include a releasable stop to prevent the polishing pad from separating from the platen should the vacuum source be deactivated while the platen is in motion.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: December 16, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Scott E. Moore
  • Patent number: 6664920
    Abstract: A cancellation technique embodied in a system and a radar signal processing method that is employed to detect near-range targets. The present invention uses a frequency-modulation continuous-wave (FMCW) or stepped frequency waveform and is capable of detecting near-range targets that would normally be obscured by transmitter leakage and internal reflections. This cancellation technique works by transmitting one or more reference ramp signals and then subtracting the coherent average of the transmitted reference ramp signals from a group of succeeding transmitted and received ramp return -signals. The resulting group of FM ramp return signals is noncoherently integrated to achieve more stable target detection statistics. More particularly, the present technique implements the following processing steps. Generating a predetermined number of reference ramp signals. Coherently averaging target return signals corresponding to transmitted reference ramp signals to produce a reference average signal.
    Type: Grant
    Filed: November 18, 1993
    Date of Patent: December 16, 2003
    Assignee: Raytheon Company
    Inventors: Charles J. Mott, Trung T. Nguyen, Edmond E. Griffin, II
  • Publication number: 20030226764
    Abstract: Methods and apparatuses for electrochemical-mechanical processing of microelectronic workpieces. One embodiment of an electrochemical processing apparatus in accordance with the invention comprises a workpiece holder configured to receive a microelectronic workpiece, a workpiece electrode, a first remote electrode, and a second remote electrode. The workpiece electrode is configured to contact a processing side of the workpiece when the workpiece is received in the workpiece holder. The first and second remote electrodes are spaced apart from the workpiece holder. The apparatus can also include an AC power supply, a DC power supply, and a switching assembly. The switching assembly is coupled to the workpiece electrode, the first remote electrode, the second remote electrode, the AC power supply, and the DC power supply.
    Type: Application
    Filed: March 4, 2002
    Publication date: December 11, 2003
    Inventors: Scott E. Moore, Whonchee Lee, Scott G. Meikle, Trung T. Doan
  • Publication number: 20030228717
    Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GeXSe1-X) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.
    Type: Application
    Filed: June 6, 2002
    Publication date: December 11, 2003
    Inventors: Jiutao Li, Allen McTeer, Gregory Herdt, Trung T. Doan
  • Patent number: 6661306
    Abstract: A circuit layout for a lumped element dual-balun (248) where the elements of the dual-balun (248) are patterned on a monolithic substrate (250) in a compact design. The dual-balun (248) includes four inductors (252, 254, 256, 258) and four capacitors (340, 342, 360, 388) electrically coupled together to provide two zero phase RF output signals and two 180° phase RF output signals. The inductors (252, 254, 256, 258) are symmetrically disposed in a rectangular area on the substrate (250). A first pair of the inductors (252, 254) is positioned at one end of the rectangular area, and a second pair of the inductors (256, 258) is positioned at an opposite end of the rectangular area. The capacitors (340, 342, 360, 388) are formed on the monolithic substrate (250) in a central circuit area (260) between the first pair (252, 254) and the second pair of inductors (256, 258).
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: December 9, 2003
    Assignee: Northrop Grumman Corporation
    Inventors: William R. Goyette, Karl D. Peterschmidt, Trung H. Lam
  • Patent number: 6660724
    Abstract: Aminophosphonates alpha substituted by phenol groups of formula (I) have lipoprotein(a) lowering activity.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: December 9, 2003
    Assignee: Ilex Products, Inc.
    Inventors: Lan Mong Nguyen, Eric Niesor, Craig Leigh Bentzen, Hieu Trung Phan, Vinh Van Diep, Simon Floret, Raymond Azoulay, Alexandre Bulla, Yves Guyon-Gellin, Robert John Ife