Abstract: A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multi-level metal integrated circuits.

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.

Abstract: An inventive process is disclosed for creating a barrier layer on a silicon substrate of an in-process integrated circuit. The process uses MOCVD to form a metal oxide film. The source gas is preferably an organometallic compound. Ozone is used as an oxidizing agent in order to react with the source gas at a low temperature and fully volatilize carbon from the source gas. The high reactivity of ozone at a low temperature provides a more uniform step coverage on contact openings. The process is used to create etch stop layers and diffusion barriers.

Abstract: A removable memory card and an associated read/write device and its method of operation are disclosed. The memory card may be formed of a sheet of chalcogenide glass material which has memory storage locations therein defined by the locations of conductive read/write elements of the read/write device.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: A process is disclosed for creating a barrier layer on a silicon substrate of an in-process integrated circuit. The process uses MOCVD to form a metal oxide film. The source gas is preferably an organometallic compound. Ozone is used as an oxidizing agent in order to react with the source gas at a low temperature and fully volatilize carbon from the source gas. The high reactivity of ozone at a low temperature provides a more uniform step coverage on contact openings. The process is used to create etch stop layers and diffusion barriers.

Abstract: A low noise amplifier (LNA) has a selectable bypass signal path integrated into the same integrated circuit (IC) as the amplifier components. In a normal mode of operation, an integrated mode switch allows an appropriate biasing signal to be applied LNA transistors, which function to amplify an input signal and produce an amplified output signal. In an attenuation mode, which is activated to handle large input signals, the LNA transistors are switched off and the input signal is attenuated by a voltage divider, which provides an attenuated output on a signal path that bypasses the LNA amplifier. An attenuation switching signal not only operates the mode switch in the LNA, but also selects between the normal and bypass outputs of the LNA, for further amplification downstream of the LNA.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.

Abstract: A two-optic accommodative lens system. The first lens has a negative power and is located posteriorly within the capsular bag and lying against the posterior capsule. The periphery of the first optic contains a plurality of generally T-shaped haptics. The overall diameter of the first optic is slightly smaller than the capsular bag. The second optic is located anteriorly to the first optic outside of the capsular bag and is of a positive power. The peripheral edge of the second optic contains a plurality of generally T-shaped haptics and the second optic is slightly larger in overall diameter that the first optic. The haptics allow the second optic to move relative to the first optic along the optical axis of the lens system in reaction to movement of the ciliary muscle and corresponding shrinkage of the capsular bag.

Abstract: In an embodiment of the invention, a method is provided for storing multimedia information to a medium. In another embodiment, a method is provided for retrieving multimedia information stored on a medium.

Abstract: A die contacting substrate establishes ohmic contact with the die by means of raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. The arrangement may be used for establishing electrical contact with a burn-in oven and with a discrete die tester. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. A Z-axis anisotropic conductive interconnect material may be interposed between the die attachment surface and the die.

Abstract: A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In addition, the pin contacts are formed by terminal portions of the conductive members. The fabrication method includes the steps of forming the openings and the conductive members, and then thinning and etching the die to form the pin contacts. An alternate embodiment female component includes female conductive members configured to physically and electrically engage pin contacts on a mating component of a stacked assembly.

Abstract: In accordance with one embodiment, a method comprises querying, with a querying component, a print engine to ascertain one or more printmodes that are supported by the print engine, and, receiving, responsive to the querying, a list that describes printmodes supported by the print engine.

Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: An apparatus, program product and method propagate errors detected in an IO fabric element from an IO fabric that is used to couple a plurality of endpoint IO resources to processing elements in a computer. In particular, such errors are propagated to the endpoint IO resources affected by the IO fabric element in connection with recovering from the errors in the IO fabric element. By doing so, a device driver or other program code used to access each affected IO resources may be permitted to asynchronously recover from the propagated error in its associated IO resource, and often without requiring the recovery from the error in the IO fabric element to wait for recovery to be completed for each of the affected IO resources. In addition, an IO fabric may be dynamically configured to support both recoverable and non-recoverable endpoint IO resources.

Abstract: A log list comprising log identifiers is received, wherein the log list delineates a set of logs to be groomed. A log sequence number and a time-stamp are extracted from the first log record of each log in the set of logs. A system ID is extracted from a log record of each log in the set of logs. An appended log list is created wherein the system ID, time-stamp and log sequence number comprise appended information that is logically appended to each of respective ones of the log identifiers. The appended log list is sorted utilizing at least a portion of the appended information, the result comprising a sorted appended log list. An actual log sequence number is extracted from the last log record of each log in the set of logs. Each of the actual log sequence numbers is compared to a corresponding predicted log sequence number, wherein the corresponding predicted log sequence number is computed utilizing the sorted appended log list.