Abstract: A method for fabricating floating gate semiconductor devices, such as flash EEPROMs, and flash EEPROM memory arrays, is provided. The method includes providing a semiconductor substrate and forming active areas on the substrate. Each active area includes elements of a field effect transistor (FET) including a source, a drain, a channel region, and a gate dielectric layer. Trench isolation structures are also formed in the substrate for electrically isolating the active areas. In addition, a conducive layer (e.g., polysilicon) is deposited on the active areas, and chemically mechanically planarized to an endpoint of the trench isolation structures to form self aligned floating gates on the active areas. Control gate dielectric layers, and control gates are then formed on the floating gates.

Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.

Abstract: An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor.

Abstract: Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.

Abstract: A method for fabricating floating gate semiconductor devices, such as flash EEPROMs, and flash EEPROM memory arrays, is provided. The method includes providing a semiconductor substrate and forming active areas on the substrate. Each active area includes elements of a field effect transistor (FET) including a source, a drain, a channel region, and a gate dielectric layer. Trench isolation structures are also formed in the substrate for electrically isolating the active areas. In addition, a conductive layer (e.g., polysilicon) is deposited on the active areas, and chemically mechanically planarized to an endpoint of the trench isolation structures to form self aligned floating gates on the active areas. Control gate dielectric layers, and control gates are then formed on the floating gates.

Abstract: A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate w

Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.

Abstract: A method and apparatus for secure processing of cryptographic keys, wherein a cryptographic key stored on a token is processed in a secure processor mode using a secure memory. A main system processor is initialized into a secure processing mode, which cannot be interrupted by other interrupts, during a power-on sequence. A user enters a Personal Identification Number (PIN) to unlock the cryptographic key stored on the token. The cryptographic key and associated cryptographic program are then loaded into the secure memory. The secure memory is locked to prevent access to the stored data from any other processes. The user is then prompted to remove the token and the processor exits the secure mode and the system continues normal boot-up operations. When an application requests security processing, the cryptographic program is executed by the processor in the secure mode such that no other programs or processes can observe the execution of the program.

Abstract: A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

Abstract: Methods are provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). The methods include forming titanium in the contact. One method includes forming titanium by combining a titanium precursor in the presence of hydrogen, H2. Another method includes forming titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. A further method includes forming titanium by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen.

Abstract: Methods arc provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). The methods include forming titanium silicide in the contact. One method includes forming titanium silicide by combining a titanium precursor in the presence of hydrogen, H2. Another method includes forming titanium silicide by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. A further method includes forming titanium silicide by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen. The methods may further include forming titanium in the contact.

Abstract: The invention comprises particle forming methods, laser pyrolysis particle forming methods, chemical mechanical polishing slurries, and chemical mechanical polishing processes. In but one preferred implementation, a particle forming method includes feeding a first set of precursors to a first energy application zone. Energy is applied to the first set of precursors in the first energy application zone effective to react and form solid particles from the first set of precursors. Application of any effective energy to the solid particles is ceased and the solid particles and a second set of precursors are fed to a second energy application zone. Energy is applied to the second set of precursors in the second energy application zone effective to react and form solid material about the solid particles from the second set of precursors. Preferably, at least one of the first and second applied energies comprises laser energy.

Abstract: A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.

Abstract: Transmission attenuation correction device for scintigraphic cameras that contain a source of gamma rays that sweep the active surface of a detector facing it through the body of the patient in order to measure the attenuation of the photon energy through this body and therefore allow for the correction of the attenuation of the photon energy emitted by the radiated organ. The radioactive source (30) is inserted in a rod (29) located in a removable cassette (21), this rod can automatically isolate the source (30) when the cassette (21) is not in its support. Each device is contained in a box attached to the detector other than the one facing it. The rod (29) that contains the source has different realization forms that make it possible to include materials that each have their own attenuation coefficient.

Abstract: A method for fabricating floating gate semiconductor devices, such as flash EEPROMs, and flash EEPROM memory arrays, is provided. The method includes providing a semiconductor substrate and forming active areas on the substrate. Each active area includes elements of a field effect transistor (FET) including a source, a drain, a channel region, and a gate dielectric layer. Trench isolation structures are also formed in the substrate for electrically isolating the active areas. In addition, a conductive layer (e.g., polysilicon) is deposited on the active areas, and chemically mechanically planarized to an endpoint of the trench isolation structures to form self aligned floating gates on the active areas. Control gate dielectric layers, and control gates are then formed on the floating gates.

Abstract: An apparatus for dynamic termination logic of bi-directional data buses and methods of operating the same result in bi-directional data buses with improved data transfer performance. The bi-directional data bus for wire-or data transfers comprises a first end-driver coupled to a first end of the data bus configured to drive the first end of the data bus with a first signal. The second end-driver coupled to the second end of the data bus is configured to dynamically terminate the first signal from the first end-driver.

Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.

Abstract: An exemplary embodiment of the present invention discloses a method for forming a forming a storage capacitor having a uniform dielectric film, by a the steps of: forming a bottom electrode of the storage capacitor and an insulation material about the bottom electrode, the bottom electrode comprises a nitridation receptive material and the insulation material comprises a nitridation resistive material; depositing a layer of non-doped silicon to a thickness of 20 Å or less over the bottom electrode and the insulation material; converting the silicon layer to a silicon nitride compound; depositing a silicon nitride of uniform thickness directly on the silicon nitride compound while using the silicon nitride compound as a nitride-nucleation enhancing surface; exposing the silicon nitride compound and the silicon nitride layer to an oxidation ambient to form a storage capacitor dielectric film; and then forming a top electrode of the storage capacitor over the storage capacitor dielectric film.

Abstract: Integrated circuitry capacitors and methods of forming the same are described. In accordance with one implementation, a capacitor plate is formed and a conductive layer of material is formed thereover. Preferably, the conductive layer of material is more conductive than the material from which the capacitor plate is formed. In a preferred implementation, the conductive layer of material comprises a titanium or titanium-containing layer. In another preferred implementation, the capacitor plate comprises an inner capacitor plate having an outer surface with a generally roughened surface area. In one aspect of this implementation, the roughened surface area comprises hemispherical grain polysilicon. Capacitors formed in accordance with the invention are particularly well suited for use in dynamic random access memory (DRAM) circuitry.