Abstract: An improved semiconductor device structure comprises insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low-melting point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.

Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.

Abstract: The invention includes a capacitor. The capacitor has a first conductive capacitor electrode, a second conductive capacitor electrode, and a capacitor dielectric material intermediate the first and second capacitor electrodes. The dielectric material contacts both of the first and second capacitor electrodes. All of the dielectric material intermediate the first and second capacitor plates consists of silicon nitride.

Abstract: An electrostatic protection network is disclosed that may be employed in a disk drive having a magneto-resistive read element. The network comprises a ground; and an array that block a signal current flow between the read element and the ground while a signal voltage is below a predetermined value and conducts the signal current from the read element to the ground while the signal voltage is above the predetermined value. The array is formed of a N-channel and P-channel junction field effect transistors. Thus, electrostatic discharge events are dissipated through the network to diminish damage to the read element during an ESD event.

Abstract: A semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors includes, a) providing an electrically insulative device isolation mass between opposing active area regions, the insulative isolation mass having opposing laterally outermost edges; and b) providing a pair of electrically conductive transistor source/drain diffusion regions within the active area regions, one of the conductive source/drain diffusion regions being received within one of the active area regions and being associated with one field effect transistor, the other of the conductive source/drain diffusion regions being received within the other of the active area regions and being associated with another field effect transistor, the electrically conductive source/drain diffusion regions each having an outermost edge adjacent the insulative isolation mass, such source/drain diffusion regions edges being received within the respective active area reg

Abstract: A method of forming a circuitry isolation region within a semiconductive wafer comprises defining active area and isolation area over a semiconductive wafer. Semiconductive wafer material within the isolation area is wet etched using an etch chemistry which forms an isolation trench proximate the active area region having lowestmost corners within the trench which are rounded. Electrically insulating material is formed within the trench over the previously formed round corners. In accordance with another aspect, the semiconductive wafer material within the isolation area is etched using an etch chemistry which is substantially selective relative to semiconductive wafer material within the active area to form an isolation trench proximate the active area region. In accordance with still another aspect, a method of forming a circuitry isolation region within a semiconductive wafer comprises masking an active area region over a semiconductive wafer.

Abstract: A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.

Abstract: In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit.

Abstract: This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening.

Abstract: An endpoint detector and performance monitoring system for quickly and accurately measuring the change in thickness of a wafer and other planarizing parameters in chemical-mechanical polishing processes. In one embodiment, an endpoint detector has a reference platform, a measuring face, and a distance measuring device. The reference platform is positioned proximate to the wafer carrier, and the reference platform and measuring device are positioned apart from one another by a known, constant distance. The measuring face is fixedly positioned with respect to the wafer carrier at a location that allows the measuring device to engage the measuring face when the wafer is positioned on the reference platform. Each time the measuring device engages the measuring surface, it measures the displacement of the measuring face with respect to the measuring device. The displacement of the measuring face is proportional to the change in thickness of the wafer between measurements.

Abstract: A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second is conductive material from atop the first conductive layer, and leaving second conductive material atop the substrat

Abstract: A field emitter display having reduced surface leakage comprising at least one emitter tip surrounded by a dielectric region. The dielectric region is formed of a composite of insulative layers, at least one of which has fins extending toward the emitter tip. A conductive gate, for extracting electrons from the emitter tip, is disposed superjacent the dielectric region. The fins increase the length of the path that leaked electrical charge travels before impacting the gate.

Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.

Abstract: The invention encompasses methods of forming capacitors, methods of forming silicon nitride layers on silicon-comprising substrates, methods for densifying silicon nitride layers, methods for forming capacitors, and capacitors. In one aspect, the invention includes a method of densifying a silicon nitride layer comprising subjecting a silicon nitride layer to a nitrogen-comprising ambient atmosphere having at least about two atmospheres of pressure. In another aspect, the invention includes a method of forming a capacitor comprising: a) forming a first capacitor plate, the first capacitor plate comprising silicon and having a surface; b) forming a dielectric layer proximate the first capacitor plate, the dielectric layer comprising a silicon nitride layer and being formed by exposing the first capacitor plate surface to a nitrogen-comprising ambient atmosphere having at least about two atmospheres of pressure; and c) forming a second capacitor plate proximate the dielectric layer.

Abstract: Aminophosphonates alpha substituted by phenol groups of formula (I) have lipoprotein(a) lowering activity.

Abstract: A process of forming a self aligned contact on a surface of a wafer having one or more gate structures and a contact region adjacent the gate structures. The gate structures are isolated from the contact region by one or more spacers having predetermined thicknesses. The process comprises the steps of depositing a conformal etch stop layer over the gate structures and contact region, depositing a sacrificial layer over the etch stop layer, selectively removing a portion of the sacrificial layer to expose a portion of the etch stop layer adjacent the contact region and removing the etch stop layer to expose contact region. The etch stop layer protects spacers from damage resulting from selective etch of the sacrificial layer. In one preferred embodiment, the etch stop layer has a substantially uniform thickness and may be removed by a timed etch.

Abstract: A semiconductor processing method of reducing thickness depletion of a nitride layer at a junction of different underlying layers includes, a) providing a substrate, the substrate comprising a first material and a second material, the first and second materials joining at a surface junction, the first and second materials being different from one another; b) exposing the substrate to a nitrogen containing gas under pressure and elevated temperature conditions effective to nitridize an outer portion of both the first and second materials with the nitrogen containing gas to provide a nitrogen containing nucleation layer at the outer portion of both of the first and second materials over the surface junction; and c) chemical vapor depositing a nitride layer atop the nucleation layer over the first and second materials and the surface junction.