Abstract: Disclosed is a method for forming a local interconnect with a self-aligned titanium silicide process on a semiconductor substrate. The initial step of the method is to form a thin titanium layer over the electronic devices to be provided with electrical communication. A polysilicon layer is then formed over the thin titanium layer, and in a further step, an implant mask is formed over portions of the polysilicon layer so as to pattern an area where the local interconnect is desired to be formed. Ions are then implanted into the polysilicon layer exposed by the implant mask, and the implant mask is then removed. In a further step, an etch process that etches either implanted or unimplanted polysilicon and is selective to the other is conducted. The remaining implanted polysilicon and titanium layers are then annealed to form titanium silicide, and the titanium that is not converted to titanium silicide is removed.

Abstract: Powder metallurgy production of T222 alloy affording properties comparable to melt derived T222, but at higher yields and lower costs, is enabled by blending component powders of minus 325 mesh and sintering at 2,400.degree. C. in three sinter steps and utilizing a slow ramp up in the first sinter step and cold isostatic pressing prior to the first sinter step and isostatic press densification in conjunction with at least the first sinter step.

Abstract: The present invention is an endpoint detector and a method for quickly and accurately measuring the change in thickness of a wafer in chemical-mechanical polishing processes. The endpoint detector has a reference platform, a measuring face, and a distance measuring device. The reference platform is positioned proximate to the wafer carrier, and the reference platform and measuring device are positioned apart from one another by a known, constant distance. The measuring face is fixedly positioned with respect to the wafer carrier at a location that allows the measuring device to engage the measuring face when the wafer is positioned on the reference platform. Each time the measuring device engages the measuring surface, it measures the displacement of the measuring face with respect to the measuring device. The displacement of the measuring face is proportional to the change in thickness of the wafer between measurements.

Abstract: Integrated circuitry having adjacent electrically isolated field effect transistors is disclosed and which includes a bulk semiconductor substrate; an electrically insulative device isolation mass located on the substrate and positioned between opposing active area regions; a first pair of LDD diffusion regions associated with the active area and abutting against the electrically insulative device isolation mass; a pair of field effect transistors each being received within one active area; a second paid of LDD diffusion regions associated with the active area and abutting against each field effect transistor; and a pair of electrically conductive transistor source and drain diffusion regions which are respectively spaced from the insulative isolation mass and field effect transistor.

Abstract: Powder metallurgy production of Ta10W alloy affording properties comparable to melt derived Ta10W, but at higher yields and lower costs, is enabled by blending component powders of minus 325 mesh and sintering at 2,400.degree. C. in three sinter steps and utilizing a slow ramp up in the first sinter step and cold isostatic pressing prior to the first sinter step and isostatic press densification in conjunction with at least the first sinter step.

Abstract: A collimator intended to be mounted in a detector of a medical imaging system and having holes defined by a given cross section, height in inclination and vergence, as well as to a medical imaging system equipped with a collimator of this type. The holes are collected in at least a first and a second region, the holes in the first region being defined by a first cross section, a first height, a first inclination and a first vergence, the holes in the second region being defined by a second cross section, a second height, a second inclination and a second vergence, and wherein the first cross section is different than the second cross section and/or the first height is different than the second height and/or the first inclination is different than the second inclination and/or the first vergence is different than the second vergence. The invention applies, in particular, to gamma cameras.

Abstract: A semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors includes, a) providing an electrically insulative device isolation mass between opposing active area regions, the insulative isolation mass having opposing laterally outermost edges; and b) providing a pair of electrically conductive transistor source/drain diffusion regions within the active area regions, one of the conductive source/drain diffusion regions being received within one of the active area regions and being associated with one field effect transistor, the other of the conductive source/drain diffusion regions being received within the other of the active area regions and being associated with another field effect transistor, the electrically conductive source/drain diffusion regions each having an outermost edge adjacent the insulative isolation mass, such source/drain diffusion regions edges being received within the respective active area reg

Abstract: A method for providing dual booting capabilities to a computer system is disclosed. The invention facilitates the installation of a plurality of operating systems on a computer system in any order such that the computer system is able to boot from any of the installed operating systems. The invention is particularly well suited for providing dual booting capabilities in both a DOS-based operating system and Windows NT when the DOS-based operating system is installed on the computer system subsequent to installation of Windows NT.

Abstract: A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate w

Abstract: The present invention concerns a method for eliminating or reducing clock skew introduced by differing signal propagation delays across a data bus. At high bus clock frequencies the time delay differences caused by path length differences can be catastrophic and must be eliminated by expensive layout techniques. An input/output (I/O) architecture is proposed here which tailors a delay to each individual data line, and thereby aligns all the incoming data. Furthermore, a clock signal is provided to indicate the optimal data sampling time. In the described embodiment, this circuit enables the transmission of four 32 bit words in parallel in one clock cycle of a 250 MHz processor.

Abstract: A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.

Abstract: An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate. The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor.

Abstract: A method of auditing login activity in a distributed computing environment in which users attempt to log into the environment from workstations using an authentication protocol in which a ticket request and pre-authentication data are communicated from the workstation to an authentication server. The pre-authentication data includes information establishing an identity of the user and providing a proof that the user has entered a password during the login attempt. The method is effected as a background process during the login, and is initiated after the ticket has been returned to the workstation from the authentication server to avoid RPC deadlock. To audit the login, information from the pre-authentication data is used to obtain a simple name of the user. The simple name is then converted into a global format and evaluated. If the name is recognized, it is passed along with the workstation address to an audit API. If the name is invalid, the audit is suspended.

Abstract: The present invention teaches electroless liquid vapor deposition/etching process for depositing on a reactive or non-reactive substrate surface or etching a film on a substrate surface in a bathless deposition apparatus during ULSI processing by the steps of: applying liquid chemical precursor solutions to the surface of the substrate, the liquid chemical precursor solutions are reactive to one another and enter the chamber of the inert atmosphere deposition apparatus separately; spinning the substrate during the application of the liquid chemical precursor solutions; and depositing or etching the film. The process may be implemented in inert atmosphere by enclosing the whole arrangement in a chamber and flowing inert gases such as Ar, He, and N.sub.2, etc.

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.

Abstract: A centrifuge having a housing defining a chamber features a containment system with a decelerator to reduce the kinetic energy of debris traveling from the chamber toward the housing. The chamber includes an opening, and a lid is pivotally mounted to the housing to selectively cover the opening. The decelerator includes a first annular member extending from a periphery of the opening inwardly toward the chamber, terminating in a downwardly extending angled region, as well as a second annular member extending downwardly in spaced relation with respect to the housing, forming a gap therebetween. The second annular member, the first annular member and the annular gap define a trap adapted to preventing debris from impinging upon the gasket and the lid. An annular baffle extends downwardly from the lid and is adapted to seat proximate to the trap upon the lid being positioned to cover the opening.

Abstract: A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: Methods for separation of wheat flour into protein and starch fractions are described. Wheat flour is (1) mixed with water to hydrate the flour and form a cohesive batter or dough, (2) chilled, and (3) mixed and washed with chilled ethanol to separate it into protein and starch fractions. Wheat protein fractions that are equivalent in yield and protein concentration to fractions produced by water washing methods are obtained, while reducing water and energy use. The protein fraction showed improved dough strength.

Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and a controller selectively adjusting one of a plurality of adjustable polishing parameters during polishing of the wafer.

Abstract: A method of passivating an outer portion of a semiconductor wafer comprises: a) applying and patterning a metal layer to define conductive metal runners projecting atop the wafer, the conductive metal runners projecting outwardly from the wafer at given distances; b) applying an insulating dielectric layer atop the wafer to a thickness which is greater than the given distance of a furthest projecting metal runner; c) global planarizing the insulating dielectric layer to some point on the wafer which is elevationally above the underlying conductive metal runners; the preferred method is by chemical mechanical polishing; and d) applying a planar layer of an effective mechanical protection, chemical diffusion barrier and moisture barrier material atop the globally planarized layer of insulating dielectric.