Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

Abstract: A computer using a passive backplane internal architecture is provided. In particular, a CPU board is provided that has a plurality of I/O interfaces (e.g., IDE, EIDE, SCSI, wide SCSI, etc.) so as to reduce the need to upgrade the system over time. However, once repair or upgrade is needed, the plug-in board configuration of the computer greatly facilitates such activity, which reduces the need for specialized (and expensive) technicians to maintain the computer. The power supply of the computer is preferably provided on an additional board within the computer. This improves the airflow of cooling air in the computer, thereby enhancing system reliability.

Abstract: A process of forming a capacitor on a surface of a wafer having one or more word lines and an active area adjacent the word lines. The word lines are isolated from the active areas by isolation spacers. The process comprises the steps of forming a multilayer structure over the word lines and the active area, selectively removing a portion of the multilayer structure to expose active area and to form a capacitor container region above the active area and sequentially depositing the bottom electrode, the cell dielectric and the upper electrode of the capacitor. The multilayer structure comprises a conformal etch stop layer, a sacrificial layer and a mask layer. The etch stop layer protects the active area and word line spacers during a selective etch of the sacrificial layer, and the etch stop layer may then be removed with minimal damage to the gate electrode spacers. In the preferred embodiment, the process requires only two masking steps to form a fully isolated, high-surface area capacitor for a DRAM cell.

Abstract: The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a CMP process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the CMP process utilizes a system of closely regulating the timing of the two chemical processes. Specifically, during a first time period, both chemicals are applied; thus providing a given speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, so as to slow down the chemical action and facilitate a greater degree of planarization.

Abstract: A method and system are provided for implementing virtual local area networks (VLANs) over ATM using LAN over ATM emulation technology. Server nodes which provide address registration/resolution and which enable multicast and broadcast routing on each VLAN are interconnected into multiple trees. The root server nodes of each tree are interconnected according to a hypercube topology. Data structures for maintaining the locations and routing information of mobile terminals is provided. Methods for constructing and updating the data structures when a mobile terminal moves from location to another also provided. Methods are also provided for routing packets using the data structures to and from mobile terminals.

Abstract: A cart for unloading and transporting chain is provided. The cart includes a frame with a number of tracks of a predetermined configuration which are superimposed over one another. Long segments of chain are routed from an oven onto a transfer rail assembly which, in turn, routes the segment of chain to a given track mounted in the cart. Subsequent segments are similarly routed to other tracks in the cart after the cart is elevated to register the empty track to be loaded with the corresponding transfer rail. As a result, the unloading and transporting chain for rebuild and repair is significantly simplified while reducing the overall time and burden associated therewith.

Abstract: A secret-key block-cipher utilizing the principles of factorization and composition with respect to general logarithmic signatures in permutation groups of arbitrary size 2.sup.l, and methods of use thereof are disclosed. The preferred embodiment uses two encryption/decryption stages from composition and factorization means including novel and efficient circuits for multiplication and inversion of permutations, operating in their compact form representation. The system is scalable to any input/output block size l and performs encryption/decryption at very high data rates.

Abstract: A device for generating high frequency power comprises an AC to DC converter comprising an AC to DC input and AC to DC output, a step down converter comprising a step down input and a step down output, said step down input coupled to the AC to DC output, a radio frequency amplifier comprising a RF input and a RF output, the RF input coupled to said step down output, a first winding comprising a first terminal and a second terminal, the first terminal and said second terminal coupled to said RF output; and a second winding magnetically coupled to said first winding.

Abstract: A method of passivating an outer portion of a semiconductor wafer comprises: a) applying and patterning a metal layer to define conductive metal runners projecting atop the wafer, the conductive metal runners projecting outwardly from the wafer at given distances; b) applying an insulating dielectric layer atop the wafer to a thickness which is greater than the given distance of a furthest projecting metal runner; c) global planarizing the insulating dielectric layer to some point on the wafer which is elevationally above the underlying conductive metal runners; the preferred method is by chemical mechanical polishing; and d) applying a planar layer of an effective mechanical protection, chemical diffusion barrier and moisture barrier material atop the globally planarized layer of insulating dielectric.

Abstract: A process of forming a self aligned contact on a surface of a wafer having one or more gate structures and a contact region adjacent the gate structures. The gate structures are isolated from the contact region by one or more spacers having predetermined thicknesses. The process comprises the steps of depositing a conformal etch stop layer over the gate structures and contact region, depositing a sacrificial layer over the etch stop layer, selectively removing a portion of the sacrificial layer to expose a portion of the etch stop layer adjacent the contact region and removing the etch stop layer to expose contact region. The etch stop layer protects spacers from damage resulting from selective etch of the sacrificial layer. In one preferred embodiment, the etch stop layer has a substantially uniform thickness and may be removed by a timed etch.

Abstract: A pad refurbisher that provides in situ, real-time conditioning and/or cleaning of a polishing surface on a polishing pad used in chemical-mechanical polishing of a semiconductor wafer and other microelectronic substrates. The pad refurbisher has a body adapted for attachment to a wafer carrier of a chemical-mechanical polishing machine, and a refurbishing element connected to the body. The body has a distal face positioned proximate to a perimeter portion of the wafer carrier and facing generally toward the polishing surface of the polishing pad. The body travels with the wafer carrier as the wafer carrier moves over the polishing pad. The refurbishing element is connected to the distal face of the body so that the refurbishing element can operatively engage the polishing surface substantially adjacent to the perimeter of the wafer carrier.

Abstract: A questionless case-based knowledge base suitable for access by an intelligent search engine and an associated method for constructing the same from pre-existing on-line documentation. A case structure for questionless cases is determined. The determined case structure includes a first field for containing a title for a case, a second field for containing a description of the case and a third field for containing a solution for the case. On-line documentation having information directed to a plurality of topics, each of which includes a title portion and a contents portion, is then provided. The information directed to each of the plurality of topics is then reconfigured into the determined case structure such that the title portion of each topic is configured as a first field of a corresponding case and the contents portion of each topic is configured as a second field of the corresponding case.

Abstract: The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the cmp process utilizes a system of closely regulating the timing of the two chemical process. Specifically, during a first time period, both chemicals are applied; thus increasing speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, thus slowing down the chemical action and importantly achieving a greater degree of planerization than is capable by the two chemical first time period.

Abstract: A polishing pad for use in chemical-mechanical planarization (CMP) of semiconductor wafers includes a multiplicity of elongated microcolumns embedded in a matrix material body. The elongated microcolumns are oriented parallel to each other and extend from a planarizing surface used to planarize the semiconductor wafers. The elongated microcolumns are uniformly distributed throughout the polishing pad in order to impart uniform properties throughout the polishing pad. The polishing pad can also include elongated pores either coaxial width or interspersed between the elongated microcolumns to provide uniform porosity throughout the polishing pad.

Abstract: An automated bank teller machine (ATM) is provided which is characteristically easy to configure, regardless of whether a replenish-from-the-front (RFTF) configuration or a replenish-from-the-rear (RFTR) configuration is chosen. In particular, the ATM according to the present invention includes a security chest module, a top module, and an interface module. These components are common to both configurations can be built and stored in advance, and can be thereafter configured as desired. In another embodiment, an ATM is provided that permits more than one customer to use the ATM at the same time.

Abstract: This invention relates to a process for preparing biological glue components from a plasma pool which combines high recovery, quality product and viral safety. In first instance, a triple viral inactivated product comprising fibrogen, fibronectin and FXIII is obtained by treating a concentrate thereof first with a viricide solvent/detergent solution, second with viral nanofiltration, and third with heat. The recovery of a good quality product is not compromised by the process of the invention. In second instance, the same steps are reproduced for obtaining a triple viral safe thrombin product. In that case, a known proprietary process has been improved to increase the recovery of active thrombin by about two fold. One of the steps which increase the yield of thrombin is the dilution of the prothrombin solution with water 4 volumes to 1 volume prothrombin prior to acid precipitation.

Abstract: A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

Abstract: A method and apparatus for selectively conditioning a planarizing surface of a polishing pad. In one embodiment, a conditioning system has a carrier assembly with an arm that may be positioned over a polishing pad, a conditioning element coupled to the arm, and an actuator coupled to the arm to move the conditioning element into engagement with the planarizing surface of the polishing pad. The conditioning element is an abrasive member, such as an abrasive disk or a brush. The conditioning system may also have a controller operatively coupled to the engagement actuator to control an operating parameter of the conditioning element as a function of the distribution of a surface characteristic across the planarizing surface of the polishing pad.

Abstract: A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively onto the wafer and applying a suction to the area immediately surrounding the location at which the chemical is dispensed onto the wafer. Preferably, the suction is applied simultaneously with the dispensing of the chemical. One specific version of the invention provides an edge bead removal system wherein suction is applied to the area immediately surrounding the solvent dispensing nozzle to remove dissolved coating material and excess solvent from the wafer. In one aspect of this system, an apparatus for removing the edge bead includes a mechanism for dispensing a solvent selectively onto the edge of the wafer, and a mechanism surrounding the dispensing mechanism for vacuuming excess solvent and dissolved coating material from the edge of the wafer.