Patents by Inventor Trung (Tim) Trinh

Trung (Tim) Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5849628
    Abstract: A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: December 15, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung T. Doan
  • Patent number: 5842909
    Abstract: A system for polishing a semiconductor wafer, the system comprising a platen subassembly defining a polishing area; a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and means for heating the wafer while the wafer face is being polished.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: December 1, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung Tri Doan
  • Patent number: 5824576
    Abstract: A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate w
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: October 20, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Charles H. Dennison
  • Patent number: 5805686
    Abstract: A fraud detection system is disclosed for telephone PBX calls. The system includes a fraud data server for buffering the call detail records relating to inbound 800 number calls and outbound international calls. A threshold manager is connected at its input to an output of the fraud data server for detecting numerical counts exceeding preselected threshold values, in predetermined fields of the call detail records, and generates an alarm. The output of the threshold manager is connected to an input of the fraud data server for buffering the alarm incident to respective call detail records. A computer workstation is connected to the fraud data server for receiving packets of call detail records relating to alarm data, in a filtered preselected format. The workstation includes a monitor for displaying the alarm data on a graphical interface.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: September 8, 1998
    Assignee: MCI Corporation
    Inventors: Jens L. Moller, Matthew L. Galetti, Terrill J. Curtis, Trung Mai
  • Patent number: 5795218
    Abstract: A polishing pad for use in chemical-mechanical planarization (CMP) of semiconductor wafers includes a multiplicity of elongated microcolumns embedded in a matrix material body. The elongated microcolumns are oriented parallel to each other and extend from a planarizing surface used to planarize the semiconductor wafers. The elongated microcolumns are uniformly distributed throughout the polishing pad in order to impart uniform properties throughout the polishing pad. The polishing pad can also include elongated pores either coaxial width or interspersed between the elongated microcolumns to provide uniform porosity throughout the polishing pad.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: August 18, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Scott G. Meikle
  • Patent number: 5786720
    Abstract: A driver circuit that is powered by a power supply voltage has an output terminal, and includes a pull-up transistor for pulling the output terminal up toward the power supply voltage. A voltage divider that is connected across the power supply voltage has a tap connected in circuit to an input of the pull-up transistor and includes variable resistance elements whose resistance varies together with a threshold voltage of the pull-up transistor for limiting a voltage at the output terminal to within a predetermined range that is lower than the power supply voltage.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: July 28, 1998
    Assignee: LSI Logic Corporation
    Inventors: Trung Nguyen, Dien Ngo
  • Patent number: 5786632
    Abstract: A method for packaging a semiconductor die includes forming an additional protective layer and conductive traces on the die. The die is then placed in a multi-die holder having electrical connectors for establishing an electrical connection to the conductive traces. The protective layer is formed as a thin or thick film of an electrically insulating material such as a polymer, glass, nitride or oxide. In addition, the protective layer can be formed with a tapered peripheral edge to facilitate insertion of the die into the die holder.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: July 28, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan, John O. Jacobson
  • Patent number: 5781022
    Abstract: A die contacting substrate for establishing ohmic contact with the die is formed with raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. In the preferred embodiment, the substrate is formed of semiconductor material, with the raised portion being formed by etching. The arrangement may be used for establishing temporary electrical contact and with a burn-in oven and with a discrete die tester. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. A Z-axis anisotropic conductive interconnect material may be interposed between the die attachment surface and the die.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: July 14, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Trung Tri Doan, Warren M. Farnworth, Tim J. Corbett
  • Patent number: 5780855
    Abstract: A gamma camera equipped with at least two radiation detectors inclined in relation to each other and a patient-carrier bed including a platform which includes a window that is more transparent to radiation than the rest of the platform. The platform includes two parts defining the window therebetween and connected to each other by a lateral arch.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: July 14, 1998
    Assignee: SMV International
    Inventors: Christian Pierre Pare, Quang Trung Nguyen, Gerard Mercier
  • Patent number: 5777739
    Abstract: The present invention is an endpoint detector and a method for quickly and accurately measuring the change in thickness of a wafer in chemical-mechanical polishing processes. The endpoint detector has a reference platform, a measuring face, and a distance measuring device. The reference platform is positioned proximate to the wafer carrier, and the reference platform and measuring device are positioned apart from one another by a known, constant distance. The measuring face is fixedly positioned with respect to the wafer carrier at a location that allows the measuring device to engage the measuring face when the wafer is positioned on the reference platform. Each time the measuring device engages the measuring surface, it measures the displacement of the measuring face with respect to the measuring device. The displacement of the measuring face is proportional to the change in thickness of the wafer between measurements.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: July 7, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Trung Tri Doan
  • Patent number: 5777354
    Abstract: An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first reduced from the prior art cell heights, and the width of the cell is then varied according to the particular need of the circuit. When the drive strength of the I/O circuit is high, and the circuit is more complicated, a wider cell is assigned. Conversely, for a circuit that is relatively simple, a narrower cell will be assigned. Each I/O cell has one associated bonding pad which is placed directly below the starting point of that cell. The height of the cells may also be varied on each side of the chip in order to be able to place more I/O cells along one or more sides or edges of the chip.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: July 7, 1998
    Assignee: LSI Logic Corporation
    Inventors: Gary H. Cheung, Elias Lozano, Trung Nguyen, Michael J. Colwell, Kevin Atkinson
  • Patent number: 5767005
    Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: June 16, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Tyler A. Lowrey
  • Patent number: 5762537
    Abstract: A system for polishing a semiconductor wafer, the system comprising a platen subassembly defining a polishing area; a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face; and means for heating the wafer while the wafer face is being polished.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: June 9, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung Tri Doan
  • Patent number: 5756565
    Abstract: Non-gellable, high temperature storage-stable bitumen/polymer compositions are provided and which are produced by stirring a sulphur-cross-linkable elastomer, an antigelling adjuvant and a sulphur-donating coupling agent into a bitumen or bitumen mixture at 100.degree.-230.degree. C. The antigelling adjuvant has the formula R--X wherein R is a C.sub.2-50 monovalent organic radical and X is a carboxylic acid, sulfonic acid or phosphoric acid group. The bitumen-polymer compositions may be used directly or in diluted form in a bitumen or bitumen mixture to form bitumen/polymer binders for producing road surfaces, coating materials or sealing materials.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: May 26, 1998
    Assignee: Elf Antar France
    Inventors: Laurent Germanaud, Jean-Pascal Planche, Trung Kiet Phung
  • Patent number: 5754060
    Abstract: An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: May 19, 1998
    Inventors: Trung Nguyen, Anthony Yap Wong
  • Patent number: 5742252
    Abstract: An apparatus for reducing the computational requirements for resolving ambiguity in interferometer measurements where the interferometer elements are arranged arbitrarily. Each of a plurality of interferometer elements each measures the phase of the incoming electromagnetic signal. The interferometer elements are each separated by lengths defined as baselines, which are sorted and processed in ascending order. Following initialization, for each baseline (92, 108), the phase measurements of the next baseline (92, 108) to be processed are estimated. If the measured phases (94-100, 110-118) of the next baseline (92, 108) falls within a predetermined range (104, 106) of the estimated phases, the phase is retained for estimating the phases of the next baseline. After a sufficient number of baselines have been processed, the angle of the incoming electromagnetic signal may be determined in accordance with the retained phases.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: April 21, 1998
    Assignee: Raytheon Company
    Inventors: Trung T. Nguyen, Loan Taree Bui
  • Patent number: 5738562
    Abstract: A chemical-mechanical polishing apparatus includes a slurry-wetted polishing pad attached to a substantially planar surface of a platen. A wafer carrier is positioned in close proximity to the platen, and it has a substantially planar surface to which one side of a semiconductor wafer is removably attachable so that an opposing side of the semiconductor wafer is disposed against the polishing pad. An actuator imparts a translational motion to the platen so that the polishing pad moves relative to and in polishing contact with the semiconductor wafer. A sensor detects a change in the imparted translational motion corresponding to a change in the coefficient of friction between the polishing pad and the opposing side of the semiconductor wafer indicative of a planar end point on the opposing side of the semiconductor wafer. The sensor preferably includes a laser and a laser detector using a laser reflection or laser interferometric method to detect the change in the imparted translational motion.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: April 14, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Gurtej Singh Sandhu, Malcolm K. Grief
  • Patent number: 5730642
    Abstract: A system for polishing a semiconductor wafer, the system comprising a wafer polishing assembly for polishing a face of a semiconductor wafer at a polishing rate and a polishing uniformity, the wafer polishing assembly including a platen subassembly defining a polishing area, a slurry supply system delivering a slurry to the polishing area, and a polishing head selectively supporting a semiconductor wafer and holding a face of the semiconductor wafer in contact with the platen subassembly; and an optical measurement system measuring film thickness at multiple different locations on the wafer face while the wafer is under a liquid, wherein drying of the wafer is avoided while the measurements are taken.
    Type: Grant
    Filed: January 30, 1997
    Date of Patent: March 24, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Trung Tri Doan
  • Patent number: 5723382
    Abstract: This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening.
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: March 3, 1998
    Inventors: Gurtej S. Sandhu, Trung T. Doan, Tyler A. Lowrey
  • Patent number: D392927
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: March 31, 1998
    Inventor: Trung Luong