Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.

Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.

Abstract: The present invention is a cardioplegic solution that demonstrates better stability in pH, particulate matter formation and osmolality but at the same time demonstrates superior ability to preserve heart functions than currently available cardioplegic solutions. The cardioplegic solution comprises potassium (K+), magnesium (Mg2+), sodium (Na+), chloride (Cl?), gluconate, acetate, sulfate (SO42?), THAM and mannitol dissolved in water.

Abstract: A method is provided for restoring an electrolyte of vanadium (V) redox flow battery (VRFB). Electrolyte data of an original system are analyzed in advance. A reusable positive electrode is further equipped with a V electrolyte. A reductant for a stack of VRFB is used in coordination as an electrolysis device. After a long-term reaction with a VRFB having a high valence (greater than 3.5), an electrolyte at the positive electrode is directed out to a negative electrode of the electrolysis device; and, then, electrolysis is processed after accurate calculation. In the end, the internal fluid balancing method of the original system is combined. Thus, a harmless and quick valence restoration is processed for the electrolyte of the original system, which is a final resort for the restoration of V electrolyte.

Abstract: A radar module includes a printed circuit board (PCB) and a semiconductor package mounted on the PCB. The semiconductor package comprises an integrated circuit die and a substrate for electrically connecting the integrated circuit die to the PCB. The substrate comprises an antenna layer integrated into the semiconductor package and electrically connected to the integrated circuit die for at least one of transmitting and receiving radar signals. A discrete pattern-shaping device is mounted on the PCB and is configured to shape a radiation pattern of the radar signals.

Abstract: One wireless communication device includes a transmitter circuit and a control circuit, wherein the control circuit sets a request to send (RTS) frame, and controls the transmitter circuit to transmit the RTS frame via at least one channel excluding a preamble punctured channel. Another wireless communication device includes a transmitter circuit and a control circuit, wherein the control circuit sets an RTS frame, and controls the transmitter circuit to transmit the RTS frame via a plurality of channels including the preamble punctured channel.

Abstract: An integrated circuit including a substrate, a first semiconductor element, and a second semiconductor element is provided. The substrate has a high voltage region and a low voltage region separated from each other. The first semiconductor element is located in the high voltage region. The first semiconductor element includes a first oxide layer and a first gate. The first oxide layer is embedded in the substrate. The first gate is located on the first oxide layer. The first gate is a polycrystalline gate. The second semiconductor element is located in the low voltage region. The second semiconductor element includes a second oxide layer and a second gate. The second oxide layer is embedded in the substrate. The second gate is located on the second oxide layer. The second gate is a metal gate. A manufacturing method of an integrated circuit is also provided.

Abstract: A radar module includes a printed circuit board (PCB) and a semiconductor package mounted on the PCB. The semiconductor package comprises an integrated circuit die and a substrate for electrically connecting the integrated circuit die to the PCB. The substrate comprises an antenna layer integrated into the semiconductor package and electrically connected to the integrated circuit die for at least one of transmitting and receiving radar signals. A discrete pattern-shaping device is mounted on the PCB and is configured to shape a radiation pattern of the radar signals.

Abstract: A probe head includes a probe seat, a first spring probe penetrating through upper, middle and lower dies of the probe seat for transmitting a first test signal, and at least two shorter second spring probes penetrating through the lower die for transmitting a second test signal with higher frequency. Two second spring probes are electrically connected in a way that top ends thereof are abutted against two electrically conductive contacts on a bottom surface of the middle die electrically connected by a connecting circuit therein. The lower die has a communicating space and at least two lower installation holes communicating therewith and each accommodating a second spring probe partially located in the communicating space. The probe head is adapted for concurrent high and medium or low frequency signal tests, meets fine pitch and high frequency testing requirements and prevents probe cards from too complicated circuit design.

Abstract: A wireless communication terminal including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from an AP. The controller is coupled to the wireless transceiver, and is operable to configure the wireless communication terminal to operate as a non-AP STA, and transmit a MU PPDU with a single RU spanning a partial bandwidth of the MU PPDU to the AP via the wireless transceiver. In particular, the partial bandwidth excludes a frequency band of a primary channel.

Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.

Abstract: A storage module of distributed flow battery is provided. An electrochemical reaction is processed with the positive and negative electrolytes to produce and/or discharge direct current and further output the positive and negative electrolytes after the reaction. The module comprises two end plates; two frames disposed between the two end plates; two current collectors disposed between the two frames; two complex cast polar plates disposed between the two current collectors; two electrodes disposed between the two complex cast polar plates; a membrane disposed between the two electrodes; and three gaskets. Therein, two of the gaskets are set to sandwich and enclose one of the two complex cast polar plates; and the other one of the gaskets is set between the other one of the two complex cast polar plates and an adjacent one of the current collectors.

Abstract: A method is provided for restoring an electrolyte of vanadium (V) redox flow battery (VRFB). Electrolyte data of an original system are analyzed in advance. A reusable positive electrode is further equipped with a V electrolyte. A reductant for a stack of VRFB is used in coordination as an electrolysis device. After a long-term reaction with a VRFB having a high valence (greater than 3.5), an electrolyte at the positive electrode is directed out to a negative electrode of the electrolysis device; and, then, electrolysis is processed after accurate calculation. In the end, the internal fluid balancing method of the original system is combined. Thus, a harmless and quick valence restoration is processed for the electrolyte of the original system, which is a final resort for the restoration of V electrolyte.

Abstract: An Antenna-in-Package (AiP) includes an interface layer having at least an antenna layer and an insulating layer disposed under the antenna layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. An integrated circuit die is disposed on the interface layer. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region includes a first antenna element, a second antenna element extending along a first direction, and a feeding network electrically connecting the first antenna element and the second antenna element to the integrated circuit die. The feeding network, the first antenna element, and the second antenna element are coplanar. A plurality of solder balls is disposed on a surface of the interface layer.