Abstract: A fingerprint recognition device with a wake-up function is provided, which includes a signal wiring, a sensing array at least partially surrounded by the signal wiring, a first electrode, and a control circuit. The control circuit is coupled with the signal wiring, the first electrode, and the sensing array. The control circuit detects capacitance between the signal wiring and the first electrode in a first operation mode to generate a sensing result, and determines whether an object is on or near the sensing array according to the sensing result. If the control circuit determines that the object is on or near the sensing array, the control circuit switches from the first operation mode to a second operation mode. The control circuit drives the sensing array by the signal wiring to generate multiple sensing signals in the second operation mode, and calculates a sensed image according to the multiple sensing signals.

Abstract: The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.

Abstract: A method for forming glass ceramic articles includes heating a stack of glass sheets to a nucleation temperature to create a nucleated crystallizable stack of sheets; heating the nucleated crystallizable stack of glass sheets to a crystallization temperature; and maintaining the crystallization temperature for a predetermined period of time to produce the glass-ceramic articles. The stack of glass sheets has a mass index of less than or equal to 35.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

Abstract: A semiconductor package includes a bottom chip package having a first side and a second side opposing the first side. The bottom chip package comprises a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. A top antenna package is mounted on the first side of the bottom chip package. The top antenna package comprises a radiative antenna element. A connector is disposed on the second side.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

Abstract: An Antenna-in-Package (AiP) includes an interface layer having at least an antenna layer and an insulating layer disposed under the antenna layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. An integrated circuit die is disposed on the interface layer. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region includes a first antenna element, a second antenna element extending along a first direction, and a feeding network electrically connecting the first antenna element and the second antenna element to the integrated circuit die. The feeding network, the first antenna element, and the second antenna element are coplanar. A plurality of solder balls is disposed on a surface of the interface layer.

Abstract: A dustproofing device for use with a linear module includes a dustproofing band disposed around a first pulley pivotally connected to a first end unit and a second pulley pivotally connected to a second end unit. Two ends of the dustproofing band fixedly connect to a fixing platform. The fixing platform fixedly connects to a moving platform of the linear module. A top lid is fixedly disposed on the first end unit and the second end unit and covers the fixing platform, so as for the dustproofing device to be mounted on the linear module. Since the linear module is covered with the first end unit, a first lateral lid, the second end unit and the top lid, not only is the linear module rendered dustproof, but it also takes less time than before to mount the dustproofing device in place.

Abstract: A gate structure of split-gate MOSFET includes a substrate, an epitaxial layer, a first gate, a second gate, a bottom dielectric layer between the first gate and the epitaxial layer, a gate dielectric layer between the second gate and the epitaxial layer, and an inter-gate dielectric layer between the first and second gates. The epitaxial layer is on the substrate having first and second trenches with different extending directions, wherein the first trench and the second trench have an overlapping region. The width of the first trench is greater than that of the second trench. The depth of the first trench is greater than that of the second trench. The first gate is in the first trench. The second gate is in the first trench on the first gate and in the second trenches.

Abstract: An Antenna-in-Package (AiP) includes an interface layer, an integrated circuit die disposed on the interface layer, a molding compound disposed on the interface layer and encapsulating the integrated circuit die, and a plurality of solder balls disposed on a bottom surface of the interface layer. The interface layer includes an antenna layer, and an insulating layer between the antenna layer and the ground reflector layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region is disposed adjacent to a first edge of the integrated circuit die, and the second antenna region is disposed adjacent to a second edge of the integrated circuit die, which is opposite to the first edge.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.

Abstract: A timing calibration system is applicable to a memory read system which includes a memory, a delay unit and a data read circuit. The memory outputs a data signal and a data latch signal. The delay unit delays the data latch signal by a delay value, to generate a read signal. The data read circuit reads the data signal according to the read signal. In the timing calibration system, a logic computation unit generates first and second charging signals according to the data signal and the read signal, and a capacitor-resistor charging unit performs charging operations according to the first and second charging signals, so as to generate first and second capacitor voltages, and a comparing unit can compare the first and second capacitor voltages, to generate a comparison result, thereby adjusting the delay value of the delay unit according to the comparison result.

Abstract: A timing calibration system is applicable to a memory read system which includes a memory, a delay unit and a data read circuit. The memory outputs a data signal and a data latch signal. The delay unit delays the data latch signal by a delay value, to generate a read signal. The data read circuit reads the data signal according to the read signal. In the timing calibration system, a logic computation unit generates first and second charging signals according to the data signal and the read signal, and a capacitor-resistor charging unit performs charging operations according to the first and second charging signals, so as to generate first and second capacitor voltages, and a comparing unit can compare the first and second capacitor voltages, to generate a comparison result, thereby adjusting the delay value of the delay unit according to the comparison result.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: A Radio Frequency (RF) device may include a plurality of antennas and one or more conductive traces configured to trap a portion of energy transmitted from at least one of the plurality of antennas. The one or more conductive traces are sized and positioned such that undesired coupling between the plurality of antennas may be suppressed while maintaining performance parameters of at least one of the plurality of antennas. The plurality of antennas and the one or more conductive traces may be formed using a redistribution layer coupled to a chip embedded in a molding layer.

Abstract: A wireless charging device with a heat dissipation function is provided. The wireless charging device includes a case, a wireless charging assembly and a working fluid. The case includes an accommodation space. The wireless charging assembly is disposed in the accommodation space. The wireless charging assembly includes a circuit board, a coil coupled to the circuit board and a connector coupled to the circuit board. The working fluid is disposed in the accommodation space in the case. The circuit board and the coil of the wireless charging assembly are immersed in the working fluid.

Abstract: A touch-controlled assembly adapted to an electronic device is provided. The electronic device has a front casing, a rear casing and a display surface, where the display surface is located on the front casing. The touch-controlled assembly includes a circuit board and at least one touch key. The circuit board is disposed between the front casing and the rear casing. The circuit board has at least one pad, which contacts one surface of the rear casing. The at least one touch key is disposed on another surface of the rear casing for corresponding to the at least one pad, where an orthogonal projection of the at least one touch key on the at least on pad is partially overlapped with the at least one pad.