Patents by Inventor Wen Chou

Wen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9872912
    Abstract: A method for treating pancreatic cancer is provided. The method comprises administering to a subject in need thereof a therapeutically effective amount of a pharmaceutical formulation, wherein the pharmaceutical formulation comprises (Z)-butylidenephthalide and is substantially free of (E)-butylidenephthalide.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: January 23, 2018
    Assignee: CHINA MEDICAL UNIVERSITY
    Inventors: Tzyy-Wen Chiou, Horng-Jyh Harn, Shinn-Zong Lin, Yi-Wen Chou, Mao-Hsuan Huang
  • Publication number: 20180000294
    Abstract: An electric window cleaning device includes an operating portion and a wiping portion which are attracted to both sides of a glass of a window by magnets, and are free to move along the glass by virtue of balls. The wiping portion includes a power mechanism and a power supply device. The power mechanism includes an output shaft, a rotary disc and a duster removably fixed to the rotary disc. The power device includes a switch and a battery which are electrically connected to the power mechanism. When the power mechanism is turned on, the output shaft rotates the rotary disc and the duster to clean the outer surface of the glass, as an user moves the operating portion which is attracted to the inner surface of the glass, the wiping portion will also move along the outer surface of the glass to perform cleaning operation.
    Type: Application
    Filed: June 14, 2017
    Publication date: January 4, 2018
    Inventor: WEN CHOU CHEN
  • Publication number: 20170366759
    Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.
    Type: Application
    Filed: August 14, 2017
    Publication date: December 21, 2017
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Jhih-Siou CHENG, Yi-Chuan LIU, Hung-Cheng HSIAO, Ying-Wen CHOU
  • Patent number: 9823801
    Abstract: A touch panel including a substrate, a plurality of first and second sensing series, and a plurality of conductive repairing pattern layers is provided. The first sensing series are disposed on the substrate and extended along a first direction. Each of the first sensing series includes a plurality of first sensing pads and first bridge lines, and the first bridge lines serially connect two adjacent first sensing pads. The second sensing series are disposed on the substrate and extended along a second direction. Each of the second sensing series includes a plurality of second sensing pads and second bridge lines, and the second bridge lines serially connect two adjacent second sensing pads. Each conductive repairing pattern layer electrically floating locates around the crossover region of the first and second sensing series. Two adjacent sensing pads are connected by the conductive repairing pattern layer after a repair procedure is finished.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: November 21, 2017
    Assignee: Au Optronics Corporation
    Inventors: Lih-Hsiung Chan, Shine-Kai Tseng, Chin-Yueh Liao, Hung-Wen Chou
  • Patent number: 9810579
    Abstract: A human body detecting device includes a pyroelectric infrared radial (PIR) sensor, a thermometer, a processor, an amplifying unit, and a plurality of amplification adjusting units. The PIR sensor is configured to sense infrared radiation and then generate an electronic signal. The thermometer is configured to sense an ambient temperature and then generate a temperature value. The microprocessor is electrically connected to the thermometer, and the amplifying unit is electrically connected to the pyroelectric infrared radial sensor and the microprocessor. The amplification adjusting units corresponding to a plurality of temperature intervals are electrically connected to the microprocessor and the amplifying unit. The microprocessor selects to enable one of the amplification adjusting units based on a comparison between the temperature value and the temperature intervals, such that the amplifying unit may modulate the electrical signal according to the enabled amplification adjusting unit.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 7, 2017
    Assignee: Cal-Comp Big Data, Inc.
    Inventor: Yi-Wen Chou
  • Patent number: 9812629
    Abstract: The disclosure provides a thermoelectric conversion structure and its use in heat dissipation device. The thermoelectric conversion structure includes a thermoelectric element, a first electrode and an electrically conductive heat-blocking layer. The thermoelectric element includes a first end and a second end opposite to each other. The first electrode is located at the first end of the thermoelectric element. The electrically conductive heat-blocking layer is between the thermoelectric element and the first electrode.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: November 7, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsiao-Hsuan Hsu, Chun-Hu Cheng, Ya-Wen Chou, Yu-Li Lin
  • Patent number: 9812564
    Abstract: A split-gate MOSFET includes first and second epitaxial layers, first, second, and third gates, a gate oxide layer, a trench oxide layer, and a trench implantation region formed on a substrate in order. The second epitaxial layer has a doping concentration greater than that of the first epitaxial layer. A plurality of trenches is in the first and second epitaxial layers. Both the first and second gates are located in each of the trenches in a cell region. The third gates are located in each of the trenches in a terminal region. The third gate closest to the cell region is grounded, and the others are floating. The gate oxide layer is disposed between the first and second gates. The trench oxide layer is located between the first gate and the first epitaxial layer and located between the trench surface and the third gate. The trench implantation region is located in the first epitaxial layer at the bottom of the trench and has a doping concentration less than that of the first epitaxial layer.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: November 7, 2017
    Assignee: Silicongear Corporation
    Inventors: Chih-Cheng Liu, Jiong-Guang Su, Hung-Wen Chou
  • Patent number: 9800800
    Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: October 24, 2017
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Jhih-Siou Cheng, Yi-Chuan Liu, Hung-Cheng Hsiao, Ying-Wen Chou
  • Publication number: 20170292320
    Abstract: A blind co-used sheet includes a vertical first blind sheet, a vertical second blind sheet, transverse double-layered blind sheets sown between the first and second blind sheets and fixing plate assemblies for securely holding front ends of the transverse double-layered blind sheets. The transverse double-layered blind sheets can be turned from a transverse state into a vertical state and used as a vertical blind. Alternatively, the transverse double-layered blind sheets can be 90-degree turned back from the vertical state into the transverse state and used as a Shangri-la blind. Two sides of the transverse double-layered blind sheet have upward and downward extending sunshade sections, which can overlap each other. A sunshade sheet is disposed in the transverse double-layered blind sheet to locate the blind sheets.
    Type: Application
    Filed: January 9, 2017
    Publication date: October 12, 2017
    Inventor: Tser Wen CHOU
  • Patent number: 9785005
    Abstract: A touch display panel including an active device array substrate, an opposite substrate and a liquid crystal layer is provided. The active device array substrate includes a first substrate, a black matrix, a touch-sensing device layer, a dielectric layer and an active device array layer. The black matrix is disposed on the first substrate. The touch-sensing device layer is disposed on the first substrate to cover a portion of the black matrix. The dielectric layer covers the touch-sensing device layer. The active device array layer is disposed on the dielectric layer. The touch-sensing device layer and the active device array substrate are located at two opposite sides of the dielectric layer. The liquid crystal layer is disposed between the active device array layer and the opposite substrate. Moreover, a fabricating method of the touch display panel is also provided.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 10, 2017
    Assignee: Au Optronics Corporation
    Inventors: Chia-Chun Yeh, Yu-Feng Chien, Wen-Rei Guo, Hung-Wen Chou, Chin-Chuan Liu, Po-Yuan Liu
  • Publication number: 20170287801
    Abstract: A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. A plurality of second chips are flipped on the chip bonding regions, so that second conductive bumps are located between and connected to the first inner pads and second pads of the second chips.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Applicant: ChipMOS Technologies Inc.
    Inventor: Shih-Wen Chou
  • Patent number: 9738942
    Abstract: A method for evaluating the therapeutic efficacy of interferon (IFN)/ribavirin (RBV) for hepatitis C is disclosed. The method includes the steps of providing a specimen; mixing the specimen, a primer of a miRNA Let-7g and a poly-chain reaction (PCR) reagent together; and evaluating the efficacy of IFN/RBV on inhibiting a hepatitis C virus according to the expressing level of the miRNA Let-7g in the specimen detected by the PCR reagent.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: August 22, 2017
    Assignee: KAOHSIUNG MEDICAL UNIVERSITY
    Inventors: Chia-Yen Dai, Ming-Lung Yu, Wan-Long Chuang, Wen-Wen Chou
  • Patent number: 9735092
    Abstract: A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: August 15, 2017
    Assignee: ChipMOS Technologies Inc.
    Inventors: Yu-Tang Pan, Shih-Wen Chou
  • Patent number: 9725607
    Abstract: A waterproof paint formula and a pen device for using the same. The concentration of the formula may be adjusted by changing the weight percentage of the aqueous solution and cooperate with different outlet diameter of the nibs to make the waterproof paint smoothly flow out for painting on the writings. Simultaneously, the weight percentage of Ethyl Alcohol may be adjusted to control the air-dried speed of the waterproof paint to achieve the effects of waterproof and preventing the inks or colors from diffusion.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 8, 2017
    Inventor: Wen-Chou Wu
  • Patent number: 9728479
    Abstract: A multi-chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip has a chip bonding region, a plurality of first inner pads and first outer pads. The circuit layer is disposed on the first chip and includes a plurality of insulating layers and at least one metal layer. The insulating layers have a groove disposed between the first inner pads and the first outer pads and surrounding the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip bonding region. Each first inner pad is electrically connected to a second pad of the second chip through the second conductive bump. The underfill is disposed between the first and second chips and covers the second conductive bumps.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 8, 2017
    Assignee: ChipMOS Technologies Inc.
    Inventor: Shih-Wen Chou
  • Publication number: 20170221860
    Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.
    Type: Application
    Filed: April 10, 2017
    Publication date: August 3, 2017
    Applicant: ChipMOS Technologies Inc.
    Inventor: Shih-Wen Chou
  • Patent number: 9653429
    Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: May 16, 2017
    Assignee: ChipMOS Technologies Inc.
    Inventor: Shih-Wen Chou
  • Patent number: D790958
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: July 4, 2017
    Inventor: Tser Wen Chou
  • Patent number: D791580
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 11, 2017
    Inventor: Tser Wen Chou
  • Patent number: D793765
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: August 8, 2017
    Inventor: Tser Wen Chou