Abstract: A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. A plurality of second chips are flipped on the chip bonding regions, so that second conductive bumps are located between and connected to the first inner pads and second pads of the second chips.

Abstract: A power supply for a redundant power system includes a housing, a first circuit board, a second circuit board and a cooling fan. The first and second circuit boards are sequentially disposed in the housing. The length of the first circuit board is smaller than that of the second circuit board. Between the first and second circuit boards is a gap. The first and second circuit boards are each distributed with multiple electronic elements, and are connected by at least one electrical connecting line. The electronic elements form a power supply circuit, in which a bridge rectification module is disposed on the first circuit board and close to the gap. The cooling fan is at least connected to the first circuit board and a second circuit board to locate in the gap, and directly provides the bridge rectification module with a first cooling air current when activated.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate, a semiconductor die, a base and a first inductor structure. The substrate has a die-attach surface and a solder-ball-attach surface opposite to the die-attach surface. The semiconductor die is mounted on the die-attach surface of the substrate. The semiconductor die includes a radio-frequency (RF) circuit and a first RF die pad electrically connected to the RF circuit. The base is mounted on the solder-ball-attach surface of the substrate. The first inductor structure is positioned on the substrate, the semiconductor die or the base. The first inductor structure includes a first terminal electrically connected to the first die pad and a second terminal electrically connected to a ground terminal.

Abstract: A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

Abstract: A Radio Frequency (RF) device may include a plurality of antennas and one or more conductive traces configured to trap a portion of energy transmitted from at least one of the plurality of antennas. The one or more conductive traces are sized and positioned such that undesired coupling between the plurality of antennas may be suppressed while maintaining performance parameters of at least one of the plurality of antennas. The plurality of antennas and the one or more conductive traces may be formed using a redistribution layer coupled to a chip embedded in a molding layer.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.

Abstract: A transmission method comprises: connecting a first wireless device to a second wireless device; determining by the first wireless device whether a silence time is assigned to the second wireless device; setting a communication period with the second wireless device according to the assigned silence time if the silence time assigned to the second wireless device is recorded in the first wireless device; and determining by the first wireless device the silence time according to a traffic transmitted from the second wireless device if the silence time assigned to the second wireless device is not recorded in the first wireless device.

Abstract: A method for treating pancreatic cancer is provided. The method comprises administering to a subject in need thereof a therapeutically effective amount of a pharmaceutical formulation, wherein the pharmaceutical formulation comprises (Z)-butylidenephthalide and is substantially free of (E)-butylidenephthalide.

Abstract: An electric window cleaning device includes an operating portion and a wiping portion which are attracted to both sides of a glass of a window by magnets, and are free to move along the glass by virtue of balls. The wiping portion includes a power mechanism and a power supply device. The power mechanism includes an output shaft, a rotary disc and a duster removably fixed to the rotary disc. The power device includes a switch and a battery which are electrically connected to the power mechanism. When the power mechanism is turned on, the output shaft rotates the rotary disc and the duster to clean the outer surface of the glass, as an user moves the operating portion which is attracted to the inner surface of the glass, the wiping portion will also move along the outer surface of the glass to perform cleaning operation.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: A touch panel including a substrate, a plurality of first and second sensing series, and a plurality of conductive repairing pattern layers is provided. The first sensing series are disposed on the substrate and extended along a first direction. Each of the first sensing series includes a plurality of first sensing pads and first bridge lines, and the first bridge lines serially connect two adjacent first sensing pads. The second sensing series are disposed on the substrate and extended along a second direction. Each of the second sensing series includes a plurality of second sensing pads and second bridge lines, and the second bridge lines serially connect two adjacent second sensing pads. Each conductive repairing pattern layer electrically floating locates around the crossover region of the first and second sensing series. Two adjacent sensing pads are connected by the conductive repairing pattern layer after a repair procedure is finished.

Abstract: The disclosure provides a thermoelectric conversion structure and its use in heat dissipation device. The thermoelectric conversion structure includes a thermoelectric element, a first electrode and an electrically conductive heat-blocking layer. The thermoelectric element includes a first end and a second end opposite to each other. The first electrode is located at the first end of the thermoelectric element. The electrically conductive heat-blocking layer is between the thermoelectric element and the first electrode.

Abstract: A human body detecting device includes a pyroelectric infrared radial (PIR) sensor, a thermometer, a processor, an amplifying unit, and a plurality of amplification adjusting units. The PIR sensor is configured to sense infrared radiation and then generate an electronic signal. The thermometer is configured to sense an ambient temperature and then generate a temperature value. The microprocessor is electrically connected to the thermometer, and the amplifying unit is electrically connected to the pyroelectric infrared radial sensor and the microprocessor. The amplification adjusting units corresponding to a plurality of temperature intervals are electrically connected to the microprocessor and the amplifying unit. The microprocessor selects to enable one of the amplification adjusting units based on a comparison between the temperature value and the temperature intervals, such that the amplifying unit may modulate the electrical signal according to the enabled amplification adjusting unit.

Abstract: A split-gate MOSFET includes first and second epitaxial layers, first, second, and third gates, a gate oxide layer, a trench oxide layer, and a trench implantation region formed on a substrate in order. The second epitaxial layer has a doping concentration greater than that of the first epitaxial layer. A plurality of trenches is in the first and second epitaxial layers. Both the first and second gates are located in each of the trenches in a cell region. The third gates are located in each of the trenches in a terminal region. The third gate closest to the cell region is grounded, and the others are floating. The gate oxide layer is disposed between the first and second gates. The trench oxide layer is located between the first gate and the first epitaxial layer and located between the trench surface and the third gate. The trench implantation region is located in the first epitaxial layer at the bottom of the trench and has a doping concentration less than that of the first epitaxial layer.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: A blind co-used sheet includes a vertical first blind sheet, a vertical second blind sheet, transverse double-layered blind sheets sown between the first and second blind sheets and fixing plate assemblies for securely holding front ends of the transverse double-layered blind sheets. The transverse double-layered blind sheets can be turned from a transverse state into a vertical state and used as a vertical blind. Alternatively, the transverse double-layered blind sheets can be 90-degree turned back from the vertical state into the transverse state and used as a Shangri-la blind. Two sides of the transverse double-layered blind sheet have upward and downward extending sunshade sections, which can overlap each other. A sunshade sheet is disposed in the transverse double-layered blind sheet to locate the blind sheets.

Abstract: A touch display panel including an active device array substrate, an opposite substrate and a liquid crystal layer is provided. The active device array substrate includes a first substrate, a black matrix, a touch-sensing device layer, a dielectric layer and an active device array layer. The black matrix is disposed on the first substrate. The touch-sensing device layer is disposed on the first substrate to cover a portion of the black matrix. The dielectric layer covers the touch-sensing device layer. The active device array layer is disposed on the dielectric layer. The touch-sensing device layer and the active device array substrate are located at two opposite sides of the dielectric layer. The liquid crystal layer is disposed between the active device array layer and the opposite substrate. Moreover, a fabricating method of the touch display panel is also provided.

Abstract: A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips, wherein each of the first chips has a chip bonding region, a plurality of first inner pads located in the chip bonding region and a plurality of first outer pads located outside the chip bonding region, the circuit layer includes a plurality of insulating layers, the insulating layers have at least one groove, the groove is disposed between the first inner pads and the first outer pads, and the groove surrounds the first inner pads. A plurality of second chips are flipped on the chip bonding regions, so that second conductive bumps are located between and connected to the first inner pads and second pads of the second chips.