Patents by Inventor Wen Han

Wen Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating strained-silicon metal-oxide semiconductor transistors
    Patent number: 7927954
    Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: April 19, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng, Meng-Yi Wu, Tsai-Fu Hsiao, Shu-Yen Chan
  • Semiconductor device
    Patent number: 7928512
    Abstract: A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: April 19, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Lang
  • Method of fabricating a phase-change memory
    Patent number: 7923286
    Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: April 12, 2011
    Assignees: Nanya Technology Corporation, Windbond Electronics Crop.
    Inventors: Yi-Chan Chen, Wen-Han Wang
  • IMAGE DENOISING METHOD
    Publication number: 20110069904
    Abstract: An image denoising method according to the present invention includes the steps of: sequentially selecting a pixel in an image as a current pixel; dynamically determining a current search block and a strength parameter; transferring the comparison block of each pixel in the current search block to a frequency domain; determining a current frequency basis; obtaining a similarity between each neighborhood pixel and the current pixel in the current search block according to the current frequency basis; determining a weighting of each neighborhood pixel related to the current pixel according to the strength parameter, and a distance and the current pixel in the current search block; and weighted averaging each neighborhood pixel and the current pixel in the current search block according to the weighting so as to obtain a reconstruction value of the current pixel.
    Type: Application
    Filed: July 2, 2010
    Publication date: March 24, 2011
    Applicant: PIXART IMAGING INC
    Inventors: Shu Sian YANG, Chuan Hsin LEE, Wen Han YAO
  • IMAGE DENOISING METHOD
    Publication number: 20110069902
    Abstract: An image denoising method includes the steps of: sequentially selecting a pixel in an image as a current pixel; dynamically determining a current search block and a strength parameter; pre-denoising the comparison block of each pixel in the current search block; comparing the comparison block of the pre-denoised neighborhood pixel and the comparison block of the pre-denoised current pixel to obtain a similarity between each neighborhood pixel and the current pixel in the current search block; determining a weighting of each neighborhood pixel related to the current pixel according to the strength parameter, and a distance and the similarity between each neighborhood pixel and the current pixel in the current search block; and weighted averaging each neighborhood pixel and the current pixel in the current search block according to the weighting to obtain a reconstruction value of the current pixel.
    Type: Application
    Filed: July 2, 2010
    Publication date: March 24, 2011
    Applicant: PIXART IMAGING INC
    Inventors: Shu Sian Yang, Wen Han Yao, Chuan Hsin Lee
  • Method for maintaining a smooth surface of crystallizable material
    Publication number: 20110065236
    Abstract: A method for maintaining a smooth surface of crystallizable material is disclosed. First, a substrate is provided. A target material layer is then formed on the substrate, with the target material being a crystallizable material. A protecting layer is subsequently formed on the target material layer. Next, an annealing treatment is implemented, with the surface of the target material layer, facing the protecting layer, being maintained in its original smooth state by the pressure and/or adhesion of the protecting layer. Finally, the protecting layer is removed to leave an open and smooth surface of the processed crystallizable material.
    Type: Application
    Filed: October 28, 2009
    Publication date: March 17, 2011
    Applicant: National Taiwan University
    Inventors: CHING-FUH LIN, CHA-HSIN CHAO, WEN-HAN LIN
  • Method for fabricating P-channel field-effect transistor (FET)
    Patent number: 7888223
    Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: February 15, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
  • Method of fabricating semiconductor device
    Patent number: 7888194
    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: February 15, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Li-Shian Jeng, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Kun-Hsien Lee, Meng-Yi Wu, Tzyy-Ming Cheng
  • Method of forming CMOS transistor
    Patent number: 7875520
    Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: January 25, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Meng-Yi Wu, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Kun-Hsien Lee, Li-Shian Jeng, Shih-Jung Tu, Yu-Ming Lin, Yao-Chin Cheng
  • METHOD OF FABRICATING TRANSISTORS AND A TRANSISTOR STRUCTURE FOR IMPROVING SHORT CHANNEL EFFECT AND DRAIN INDUCED BARRIER LOWERING
    Publication number: 20110012197
    Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.
    Type: Application
    Filed: July 14, 2009
    Publication date: January 20, 2011
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
  • Phase change memory device and fabricating method therefor
    Patent number: 7868314
    Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: January 11, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Su Chen, Yi-Chan Chen, Wen-Han Wang, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Te-Sheng Chao, Min-Hung Lee
  • HUMAN FACE DETECTION AND TRACKING DEVICE
    Publication number: 20100328442
    Abstract: A human face detection device includes a photosensitive element, a human face detection unit, and a skin color threshold generation unit. The photosensitive element is used for capturing a first image containing a first human face block. The human face detection unit compares the first image with at least one human face feature, so as to detect the first human face block. The skin color threshold generation unit is used for updating a skin color threshold value according to the detected first human face block. The skin color threshold value is used for filtering the first image signal to obtain a candidate region, the human face detection unit compares the candidate region with the at least one human face feature to obtain the first human face block, and the skin color threshold value determines whether the first human face block detected by the human face detection unit is correct.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 30, 2010
    Applicant: PIXART IMAGING INC.
    Inventors: Shu Sian Yang, Ren Hau Gu, Yi Fang Lee, Ming Tsan Kao, Teo Chin Chiang, Chi Chieh Liao, Wei Ting Chan, Yu Hao Huang, Wen Han Yao
  • Phase change memory cell and method of fabricating
    Patent number: 7835177
    Abstract: A phase change memory (PCM) cell fabricated by etching a tapered structure into a phase change layer, and planarizing a dielectric layer on the phase change layer until a tip of the tapered structure is exposed for contacting a heating electrode. Therefore, the area of the exposed tip of the phase change layer is controlled to be of an extremely small size, the contact area between the phase change layer and the heating electrode is reduced, thereby lowering the operation current.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: November 16, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Hong-Hui Hsu, Chien-Min Lee, Wen-Han Wang, Min-Hung Lee, Te-Sheng Chao, Yen Chuo, Yi-Chan Chen, Wei-Su Chen
  • Semiconductor MOS transistor device and method for making the same
    Patent number: 7749833
    Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: July 6, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Tzyy-Ming Cheng, Tzer-Min Shen, Yi-Chung Sheng
  • PHASE CHANGE MEMORY DEVICE AND FABRICATING METHOD THEREFOR
    Publication number: 20100140583
    Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.
    Type: Application
    Filed: August 26, 2009
    Publication date: June 10, 2010
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Su Chen, Yi-Chan Chen, Wen-Han Wang, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Te-Sheng Chao, Min-Hung Lee
  • METHOD FOR PREVIEWING OUTPUT CHARACTER AND ELECTRONIC DEVICE
    Publication number: 20100130256
    Abstract: A method for previewing an output character, and an electronic device are provided. In the present method, at least one touch signal generated by pressing at least one of the keys of a software input panel (SIP) is received. Then, an impending output character corresponding to the pressed key is determined from all relative characters thereof. Finally, showing a display window including at least the output character, and a display format of the output character in the display window is changed to specifically indicate the output character. As a result, the correctness of the pressed key on the SIP can be determined easily, and whether the impending output character is the expected character can be confirmed at the same time.
    Type: Application
    Filed: September 16, 2009
    Publication date: May 27, 2010
    Applicant: HTC CORPORATION
    Inventor: Wen-Han Yeh
  • Manufacturing Method and Structure of Night Glow Glass
    Publication number: 20100107692
    Abstract: A manufacturing method of a night glow glass includes the steps of manufacturing a small glass frit, combining a luminescent material, manufacturing a large glass frit, shaping a night glow glass and annealing, such that the luminescent material is wrapped in a glass wall of the night glow glass to prevent a color fade of the luminescent material and extend the expiration date of the night glow glass. The night glow glass of the invention can be applied in a table lamp, a garden lamp and a glass lamp house for various different illumination devices, or a decoration having a night glow effect.
    Type: Application
    Filed: November 4, 2008
    Publication date: May 6, 2010
    Inventor: Cheng-Wen Han
  • Method for forming MOS transistor
    Patent number: 7700450
    Abstract: A method for forming a MOS transistor includes providing a substrate having at least a gate structure formed thereon, performing a pre-amorphization (PAI) process to form amorphized regions in the substrate, sequentially performing a co-implantation process, a first ion implantation process, and a first rapid thermal annealing (RTA) process to form lightly doped drains (LDDs), forming spacers on sidewalls of the gate structure, and forming a source/drain.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: April 20, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Li-Shian Jeng, Tzyy-Ming Cheng
  • Method of fabricating semiconductor device
    Patent number: 7682890
    Abstract: A method of fabricating a semiconductor device is provided. A substrate is first provided, and then several IO devices and several core devices are formed on the substrate, wherein those IO devices include IO PMOS and IO NMOS, and those core devices include core PMOS and core NMOS. Thereafter, a buffer layer is formed on the substrate, and then the buffer layer except a surface of the IO PMOS is removed in order to reduce the negative bias temperature instability (NBTI) of the IO PMOS. Afterwards, a tensile contact etching stop layer (CESL) is formed on the IO NMOS and the core NMOS, and a compressive CESL is formed the core PMOS.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: March 23, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Shyh-Fann Ting, Tzyy-Ming Cheng, Chia-Wen Liang
  • Positioning structure of a single-pull reel
    Patent number: 7681823
    Abstract: A positioning rod structure for a single-pull reel which will be positioned upon pulling out of cord from the reel and will restore to its original position if the cord is pulled for a second time. When the cord is pulled for one round, a positioning of the cord is done, and the pulling of the cord provides multi control of the cord, accordingly, the pulling of cord is precisely controlled.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: March 23, 2010
    Assignee: Acrox Technologies, Co., Ltd.
    Inventor: Wen-Han Chang