Abstract: A method of manufacturing a MOS transistor, in which, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the patterned hard mask layer is used to form a gate. Thereafter, by forming and defining a cap layer, a recess is formed through etching in the substrate. The patterned hard mask is removed after epitaxial layers are formed in the recesses. Accordingly, a conventional poly bump issue and an STI oxide loss issue leading to contact bridge can be avoided.

Abstract: Disclosed is a method for manufacturing an organic optoelectronic device. The method comprises providing a substrate, disposing a first electrode on the substrate, disposing a metal pad on the substrate, electrically separated from the first electrode, disposing a first material over the first electrode and at least partially over the metal pad, applying a beam, wherein the beam ablates the first material in an ablation window so that the ablation window includes at least a portion of an edge of the metal pad, and disposing a second electrode over the first material and over the ablation window so that the second electrode is in electrical contact with the at least a portion of an edge of the metal pad.

Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.

Abstract: A positioning rod structure for a single-pull reel which will be positioned upon pulling out of cord from the reel and will restore to its original position if the cord is pulled for a second time. When the cord is pulled for one round, a positioning of the cord is done, and the pulling of the cord provides multi control of the cord, accordingly, the pulling of cord is precisely controlled.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Abstract: A method for manufacturing a MOS transistor includes performing a thermal treatment to repair damaged substrate before forming source/drain extension regions, accordingly negative bias temperature instability (NBTI) is reduced. Since the thermal treatment is performed before forming the source/drain extension regions, heat budget for forming the source/drain extension regions and junction depth and junction profile of the source/drain extension would not be affected. Therefore the provided method for manufacturing a MOS transistor is capable of reducing short channel effect and possesses a superior process compatibility.

Abstract: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

Abstract: A single-pull reel which includes a bottom cover having a center axle, a top cover engageable with the bottom cover; a cord-rotating disc having a top portion provided with a circular flange which is divided into a plurality of sections by a plurality of slots, a clamping member being provided behind one of the sections to form a passage therebetween and having a plurality of serrated teeth at an inner side against the one of the sections, the bottom portion being provided with a multi-operation urging track, a spiral spring having an inner end engaged with a notch of the axle and an outer end bent into a hook to engage with one of the sections of the cord-rotating disc, a cord, and a peg positioning structure comprising a peg and a pulling spring.

Abstract: A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

Abstract: A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.

Abstract: A positioning rod structure for a reel is disclosed. The reel is positioning upon pulling out of cord from the reel and will restore to its original position if the cord is pulled for a second time. When the cord is pulled for one round, a positioning of the cord is done, and the pulling of the cord provides multi control of the cord, accordingly, the pulling of cord is precisely controlled.

Abstract: A positioning peg structure of a single-pull reel is disclosed. The positioning structure provides the function of positioning of the cord after a second pull following the first pull of the cord. When the cord is pulled to rotate one round, a first positioning mechanism is formed. Thus, when the cord is pulled in one direction once, the cord is controlled to provide a plurality of multiple positioning such that the pulling distance can be precisely controlled.

Abstract: A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.

Abstract: Disclosed is a method for manufacturing an organic optoelectronic device. The method comprises providing a substrate, disposing a first electrode on the substrate, disposing a metal pad on the substrate, electrically separated from the first electrode, disposing a first material over the first electrode and at least partially over the metal pad, applying a beam, wherein the beam ablates the first material in an ablation window so that the ablation window includes at least a portion of an edge of the metal pad, and disposing a second electrode over the first material and over the ablation window so that the second electrode is in electrical contact with the at least a portion of an edge of the metal pad.

Abstract: A method for fabricating a semiconductor device is provided. First, a substrate is provided, and a first-type MOS (metallic oxide semiconductor) transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor are formed on the substrate. Then, a first stress layer is formed to overlay the substrate, the first-type MOS transistor, the I/O second-type MOS transistor, and the core second-type MOS transistor. Then, at least the first stress layer on the core second-type MOS transistor is removed to reserve at least the first stress layer on the first-type MOS transistor. Finally, a second stress layer is formed on the core second-type MOS transistor.

Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.

Abstract: A case structure for card-type electronic product includes an intermediate frame having insertion slots spaced thereon; a lower cover connected to a lower side of the intermediate frame by lower hooking members upward inserted into the insertion slots, and each of the lower hooking members including two spaced latch legs; and an upper cover connected to an upper side of the intermediate frame by upper hooking members downward inserted into the insertion slots corresponding to the lower hooking members, and each of the upper hooking members including two laterally outward extended latch hooks. When the upper and lower covers are assembled to the upper and lower sides of the intermediate frame, the latch hooks of the upper hooking members are abutted on lower edges of the latch legs of the lower hooking members to firmly hold the lower cover to the upper cover in three directions.

Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.

Abstract: A low profile design of multi-in-one card connector includes a base frame having two upright sidewalls and a guide groove at the front side of each upright sidewall and defining a front insertion opening, multiple terminal sets mounted in the base frame, two limiter blocks vertically movably mounted in the guide grooves of the upright sidewalls each having a top stop flange and a bottom stop flange, at least one of the top and bottom stop flanges of each limiter block being held in the front insertion opening to prohibit insertion of a second memory card after insertion of a first memory card, and two elastic members supporting the limiter blocks in an upper limit position.

Abstract: A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.