Patents by Inventor Wen Han

Wen Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making transistor having metal gate
    Patent number: 8211775
    Abstract: A method for forming a transistor having a metal gate is provided. A substrate is provided first. A transistor is formed on the substrate. The transistor includes a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on the high-k gate dielectric layer, and a dummy gate disposed on the oxygen containing dielectric layer. Then, the dummy gate and the patterned gate dielectric layer are removed. Lastly, a metal gate is formed and the metal gate directly contacts the high-k gate oxide.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: July 3, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yu Ma, Wen-Han Hung, Ta-Kang Lo, Tsai-Fu Chen, Tzyy-Ming Cheng
  • Low leakage power detection circuit
    Patent number: 8207755
    Abstract: A leakage current reduction circuit comprising a transmission gate, a feedback channel and a controller is placed between a first device supplied with a first voltage potential and a second device supplied with a second voltage potential. The voltage potential mismatch between the first device and the second device may cause a leakage current flowing through the input stage of the second device. By employing the low leakage power detection circuit, a logic high state generated from the first device can be converted into a logic high state having an amplitude approximately equal to the second voltage potential.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: June 26, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wen-Han Wang
  • THIN CABLE RETRACTOR
    Publication number: 20120138724
    Abstract: The cable retractor mainly contains a housing member, a coil spring, a rotary disc, a cable, and a winding disc. The rotary disc has a top circular indentation where the coil spring is accommodated in the indentation. A number of gear teeth are provided around the rotary disc and the winding disc. The winding disc has a central axle for the winding of the cable. The winding disc is positioned such that its teeth engage those of the rotary disc. A spiral track and a centrifugal track are provided on the rotary disc and the housing member, respectively. A positioning ball, together with the spiral track and the centrifugal track, provides a positioning function. The cable can be configured to be pulled in a single direction with a connector or multiple directors at a free end.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Inventors: KO-AN CHEN, Wen-Han Chang
  • SLIDER CASE HAVING CABLE RETRACTOR
    Publication number: 20120138725
    Abstract: The slider case provides housing for a portable appliance and integrates a cable retractor containing a coil spring, a rotary disc, a cable, and a winding disc. The rotary disc has a top circular indentation where the coil spring is accommodated in the indentation. A number of gear teeth are provided around the rotary disc and the winding disc. The winding disc has a central axle for the winding of the cable. The winding disc is positioned such that its teeth engage those of the rotary disc. A spiral track and a centrifugal track are provided on the rotary disc and the casing member, respectively. A positioning ball, together with the spiral track and the centrifugal track, provides a positioning function. The cable can be configured to be pulled in a single direction with a connector or multiple directors at a free end.
    Type: Application
    Filed: December 3, 2010
    Publication date: June 7, 2012
    Inventors: KO-AN CHEN, WEN-HAN CHANG
  • Method of fabricating transistors and a transistor structure for improving short channel effect and drain induced barrier lowering
    Patent number: 8183640
    Abstract: A method of fabricating transistors includes: providing a substrate including an N-type well and P-type well; forming a first gate on the N-type well and a second gate on the P-type well, respectively; forming a third spacer on the first gate; forming an epitaxial layer in the substrate at two sides of the first gate; forming a fourth spacer on the second gate; forming a silicon cap layer covering the surface of the epitaxial layer and the surface of the substrate at two sides of the fourth spacer; and forming a first source/drain doping region and a second source/drain doping region at two sides of the first gate and the second gate respectively.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: May 22, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Tsai-Fu Chen, Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Ta-Kang Lo, Tzyy-Ming Cheng
  • SUB-RESOLUTION ROD IN THE TRANSITION REGION
    Publication number: 20120115073
    Abstract: The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 10, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jeng-Shiun Ho, Luke Lo, Ting-Chun Liu, Min-Hung Cheng, Jing-Wei Shih, Wen-Han Chu, Cheng-Cheng Kuo, Hua-Tai Lin, Tsai-Sheng Gau, Ru-Gun Liu, Yu-Hsiang Lin, Shang-Yu Huang
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME
    Publication number: 20120086054
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a gate structure disposed on a substrate, a source and a drain respectively disposed in the substrate at two sides of the gate structure, a source contact plug disposed above the source and electrically connected to the source and a drain contact plug disposed above the drain and electrically connected to the drain. The source contact plug and the drain contact plug have relatively asymmetric element properties.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 12, 2012
    Inventors: Tzyy-Ming Cheng, Meng-Chi Tsai, Tsai-Fu Chen, Ta-Kang Lo, Wen-Han Hung, Shih-Fang Tzou, Chun-Yuan Wu
  • ADJUSTING METHOD OF CHANNEL STRESS
    Publication number: 20120070948
    Abstract: An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tzyy-Ming CHENG, Ching-Sen Lu, Tsai-Fu Chen, Wen-Han Hung, Ta-Kang Lo, Chun-Yuan Wu, Shih-Fang Tzou
  • METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20120045880
    Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.
    Type: Application
    Filed: August 23, 2010
    Publication date: February 23, 2012
    Inventors: Cheng-Yu Ma, Wen-Han Hung, Ta-Kang Lo, Tsai-Fu Chen, Tzyy-Ming Cheng
  • MARK ANTENNA AND ELECTRONIC DEVICE
    Publication number: 20120032859
    Abstract: The present invention discloses a mark antenna used for receiving and transmitting a wireless signal. The mark antenna comprises a ground point, a feed point and a radiation part connecting to the ground point and the feed point, and particularly the radiation part is an identification mark, such that the appearance of the radiation part can provide identification information. With the light, thin, short and compact design concept, the mark antenna can be exposed to prevent the antenna from being compressed due to the small disposed area and overcome the difficulty of designing the antenna or a poor communication quality caused by the low performance of the antenna. In the present invention, the antenna is designed as a logo directly, such that the antenna can achieve the functions of identifying the appearance as well as transmitting and receiving the wireless signals.
    Type: Application
    Filed: May 31, 2011
    Publication date: February 9, 2012
    Applicants: INVENTEC APPLIANCES CORP., INVENTEC APPLIANCES (SHANGHAI) CO. LTD.
    Inventor: WEN-HAN LIN
  • IMAGE CAPTURING DEVICE AND CONTROL METHOD OF OPERATION MODE THEREOF, AND ELECTRONIC DEVICE USING IMAGE CAPTURING DEVICE
    Publication number: 20120013751
    Abstract: An image capturing device includes an image capturing unit, a processing unit, a register unit, and at least one triggering unit. The image capturing unit is used for capturing image data; the processing unit is electrically connected to the image capturing unit and is used for executing a comparison procedure; the register unit is electrically connected to the processing unit and is configured with a determination logic; and the triggering unit is electrically connected to the processing unit, in which the processing unit runs the comparison procedure according to at least one of an execution state of the triggering unit and the determination logic, and the processing unit controls an operation mode of the image capturing device according to the comparison procedure.
    Type: Application
    Filed: July 14, 2011
    Publication date: January 19, 2012
    Inventors: Jiing-Horug SHIEH, Wen-Han Yao
  • METHOD FOR FABRICATING FIELD-EFFECT TRANSISTOR
    Publication number: 20120009745
    Abstract: A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure.
    Type: Application
    Filed: January 4, 2011
    Publication date: January 12, 2012
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng
  • COMPUTER MOUSE CABLE REEL STOWAGE DEVICE
    Publication number: 20110254766
    Abstract: Disclosed is a computer mouse cable reel stowage device, which ingeniously stows a computer mouse cable reel inside the structure of a computer mouse, whereby a cabled mouse and a reel that is provided for winding and releasing the mouse cable are integrated in a single combined structure to allow for easy and simultaneous carrying. Thus, the two devices of cable mouse and cable reel can be always of the simultaneity in carrying and use to ensure synergy effect of use.
    Type: Application
    Filed: April 20, 2010
    Publication date: October 20, 2011
    Inventor: WEN-HAN CHANG
  • TRANSITION METAL COMPLEXES, MANUFACTURING METHOD THEREOF, PHOTOVOLTAIC CELLS AND MANUFACTURING METHOD THEREOF
    Publication number: 20110253216
    Abstract: This invention provides a transition metal complex of formula MXY2Z and a manufacturing method thereof, wherein M is selected from iron, ruthenium, and osmium; X represents a ligand shown in formula (II) wherein R1 and R1? are independently selected from COOH, PO3H2, PO4H2, SO3H2, SO4H2, and derivatives thereof; Y is selected from H2O, Cl, Br, CN, NCO, NCS, and NCSe; Z represents a bidentate ligand having at least two fluorinated chains. In addition, this invention also provides photovoltaic cells and a manufacturing method thereof.
    Type: Application
    Filed: April 15, 2010
    Publication date: October 20, 2011
    Applicant: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Norman Lu, Jia-Sheng Shing, Wen-Han Tu
  • SEMICONDUCTOR DEVICE WITH CARBON ATOMS IMPLANTED UNDER GATE STRUCTURE
    Publication number: 20110254064
    Abstract: An exemplary semiconductor device includes a substrate, a spacer, a metal silicide layer and carbon atoms. The substrate has a gate structure formed thereon. The spacer is formed on the sidewall of the gate structure. The spacer has a first side adjacent to the gate structure and a second side away from the gate structure. The metal silicide layer is formed on the substrate and adjacent to the second side of the spacer but away from the first side of the spacer. The carbon atoms are formed into the substrate and adjacent to the first side of the spacer but away from the second side of the spacer.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng
  • Method for manufacturing semiconductor device
    Patent number: 8039330
    Abstract: The invention is directed to a method for manufacturing a semiconductor. The method comprises steps of providing a substrate having a gate structure formed thereon and forming a source/drain extension region in the substrate adjacent to the gate structure. A spacer is formed on the sidewall of the gate structure and a source/drain region is formed in the substrate adjacent to the spacer but away from the gate structure. A bevel carbon implantation process is performed to implant a plurality carbon atoms into the substrate and a metal silicide layer is formed on the gate structure and the source/drain region.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: October 18, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Li-Shian Jeng, Kun-Hsien Lee, Wen-Han Hung, Tzyy-Ming Cheng
  • Method for maintaining a smooth surface of crystallizable material
    Patent number: 8030189
    Abstract: A method for maintaining a smooth surface of crystallizable material is disclosed. First, a substrate is provided. A target material layer is then formed on the substrate, with the target material being a crystallizable material. A protecting layer is subsequently formed on the target material layer. Next, an annealing treatment is implemented, with the surface of the target material layer, facing the protecting layer, being maintained in its original smooth state by the pressure and/or adhesion of the protecting layer. Finally, the protecting layer is removed to leave an open and smooth surface of the processed crystallizable material.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: October 4, 2011
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Cha-Hsin Chao, Wen-Han Lin
  • SEMICONDUCTOR DEVICE
    Publication number: 20110156156
    Abstract: A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 30, 2011
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Liang
  • METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20110104864
    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.
    Type: Application
    Filed: January 5, 2011
    Publication date: May 5, 2011
    Inventors: Li-Shian Jeng, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Kun-Hsien Lee, Meng-Yi Wu, Tzyy-Ming Cheng
  • METHOD FOR FABRICATING P-CHANNEL FIELD-EFFECT TRANSISTOR (FET)
    Publication number: 20110097868
    Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.
    Type: Application
    Filed: January 4, 2011
    Publication date: April 28, 2011
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Meng-Yi Wu, Tzyy-Ming Cheng