Patents by Inventor Wen Han

Wen Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating a phase-change memory
    Patent number: 7670871
    Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: March 2, 2010
    Inventors: Yi-Chan Chen, Wen-Han Wang
  • METHOD OF FABRICATING A PHASE-CHANGE MEMORY
    Publication number: 20100047960
    Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.
    Type: Application
    Filed: November 2, 2009
    Publication date: February 25, 2010
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Chan Chen, Wen-Han Wang
  • Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof
    Patent number: 7662730
    Abstract: A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. The transitional silicon nitride film is subjected to UV curing process for reducing the first concentration of hydrogen atoms to a second concentration of hydrogen atoms.
    Type: Grant
    Filed: November 24, 2005
    Date of Patent: February 16, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang, Tsai-Fu Chen, Wen-Han Hung
  • Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof
    Patent number: 7655987
    Abstract: A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: February 2, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang, Tsai-Fu Chen, Wen-Han Hung
  • Case structure for card-type electronic product
    Patent number: 7649741
    Abstract: A case structure for card-type electronic product includes an intermediate frame having insertion slots spaced thereon; a lower cover connected to a lower side of the intermediate frame by lower hooking members upward inserted into the insertion slots, and each of the lower hooking members including two spaced latch legs; and an upper cover connected to an upper side of the intermediate frame by upper hooking members downward inserted into the insertion slots corresponding to the lower hooking members, and each of the upper hooking members including two laterally outward extended latch hooks. When the upper and lower covers are assembled to the upper and lower sides of the intermediate frame, the latch hooks of the upper hooking members are abutted on lower edges of the latch legs of the lower hooking members to firmly hold the lower cover to the upper cover in three directions.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: January 19, 2010
    Assignee: Sunlit Precision Technology Co., Ltd.
    Inventor: Wen-Han Liu
  • Driving method and system for a phase change memory
    Patent number: 7643373
    Abstract: An embodiment of a method for driving a phase change memory, comprising counting an access number of a phase change memory, wherein the access number is the number of times that the phase change memory has been accessed; refreshing the phase change memory when the number of times is large than a predetermined number.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: January 5, 2010
    Inventors: Shyh-Shyuan Sheu, Lieh-Chiu Lin, Pei-Chia Chiang, Wen-Han Wang
  • Method of forming metal-oxide-semiconductor transistors
    Patent number: 7642166
    Abstract: A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: January 5, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Neng-Kuo Chen, Shao-Ta Hsu, Teng-Chun Tsai, Chien-Chung Huang
  • Lateral phase change memory with spacer electrodes
    Patent number: 7626191
    Abstract: A lateral phase change memory with spacer electrodes and method of manufacturing the same are provided. The memory is formed by connecting the conductive electrodes with lower resistivity and the spacer electrodes with higher resistivity, and filling the phase change material between the spacer electrodes. Therefore, the area that the phase change material contacts the spacer electrodes and the volume of the phase change material can be reduced; thereby the programming current and power consumption of the phase change memory are reduced.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: December 1, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Te-Sheng Chao, Wen-Han Wang, Min-Hung Lee, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Yi-Chan Chen, Wei-Su Chen
  • Method of manufacturing complementary metal oxide semiconductor transistors
    Patent number: 7622344
    Abstract: A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: November 24, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Wen Liang, Cheng-Tung Huang, Shyh-Fann Ting, Chih-Chiang Wu, Shih-Chieh Hsu, Li-Shian Jeng, Kun-Hsien Lee, Meng-Yi Wu, Wen-Han Hung, Tzyy-Ming Cheng
  • Method for fabricating strained-silicon CMOS transistors
    Patent number: 7618856
    Abstract: A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is formed surrounding the first gate structure and the second gate structure. A source/drain region for the first transistor and the second transistor is formed. The first spacer is removed from the first gate structure and the second gate structure and a cap layer is disposed on the first transistor and the second transistor and the cap layer covering the second transistor is removed thereafter. An etching process is performed to form a recess in the substrate surrounding the second gate structure. An epitaxial layer is formed in the recess and the cap layer is removed from the first transistor.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: November 17, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Jing-Chang Wu, Kun-Hsien Lee, Wen-Han Hung, Li-Shian Jeng, Tzer-Min Shen, Tzyy-Ming Cheng, Nien-Chung Li
  • Single-pull power and signal cable reel
    Patent number: 7607603
    Abstract: A single-pull power and signal cable reel is disclosed. The reel provides single direction multi-stage retraction of signal and power cable. When the lead wire is pulled once, a positioning effect is provided. Accordingly, the reel allows precise control of an extended signal or cable for use in computer or related products.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: October 27, 2009
    Inventor: Wen-Han Chang
  • Structure of a single-pull reel
    Patent number: 7604194
    Abstract: A single-pull reel which includes a bottom cover having a center axle, a top cover engageable with the bottom cover; a cord-rotating disc having a top portion provided with a circular flange which is divided into a plurality of sections by a plurality of slots, a clamping member being provided behind one of the sections to form a passage therebetween and having a plurality of serrated teeth at an inner side against the one of the sections, the bottom portion being provided with a multi-operation urging track, a spiral spring having an inner end engaged with a notch of the axle and an outer end bent into a hook to engage with one of the sections of the cord-rotating disc, a cord, and a peg positioning structure comprising a peg and a pulling spring.
    Type: Grant
    Filed: December 25, 2008
    Date of Patent: October 20, 2009
    Assignee: Acrox Technologies Co., Ltd.
    Inventor: Wen-Han Chang
  • Fabricating method of CMOS
    Patent number: 7601587
    Abstract: A method of forming a metal-oxide-semiconductor (MOS) device is provided. The method includes the following steps. First, a conductive type MOS transistor is formed on a substrate. Then, a first etching stop layer is formed over the substrate to cover conformably the conductive type MOS transistor. Thereafter, a stress layer is formed over the first etching stop layer. Then, a second etching stop layer is formed over the stress layer.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: October 13, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Pei-Yu Chou, Min-Chieh Yang, Wen-Han Hung
  • Phase change memory device and fabricating method therefor
    Patent number: 7598113
    Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 6, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Su Chen, Yi-Chan Chen, Wen-Han Wang, Hong-Hui Hsu, Chien-Min Lee, Yen Chuo, Te-Sheng Chao, Min-Hung Lee
  • METHOD OF FORMING CMOS TRANSISTOR
    Publication number: 20090246922
    Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 1, 2009
    Inventors: Meng-Yi Wu, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Kun-Hsien Lee, Li-Shian Jeng, Shih-Jung Tu, Yu-Ming Lin, Yao-Chin Cheng
  • METHOD OF FORMING MOS DEVICE
    Publication number: 20090239347
    Abstract: The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated.
    Type: Application
    Filed: May 20, 2009
    Publication date: September 24, 2009
    Applicant: United Microelectronics Corp.
    Inventors: SHYH-FANN TING, Shih-Chieh Hsu, Cheng-Tung Huang, Chih-Chiang Wu, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Kun-Hsien Lee, Tzyy-Ming Cheng
  • SEMICONDUCTOR DEVICE
    Publication number: 20090224328
    Abstract: A semiconductor device includes a substrate defining an active area thereon, a shallow trench isolation on the substrate and directly surrounding the active area, a gate, a source and a drain on the active area and a hard mask on the border of the shallow trench isolation and the active area.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 10, 2009
    Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Kun-Hsien Lee, Wen-Han Hung, Meng-Yi Wu, Li-Shian Jeng, Chung-Min Shih, Tzyy-Ming Cheng, Jing-Chang Wu, Tzer-Min Shen
  • Method for forming semiconductor device
    Patent number: 7585790
    Abstract: A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: September 8, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Han Hung, Cheng-Tung Huang, Kun-Hsien Lee, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Chia-Wen Liang, Neng-Kuo Chen
  • Method of fabricating complementary metal-oxide-semiconductor transistor and metal-oxide-semiconductor transistor
    Patent number: 7582520
    Abstract: A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: September 1, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Li-Shian Jeng, Wen-Han Hung, Shyh-Fann Ting, Jing-Yi Huang, Tzyy-Ming Cheng, Chia-Wen Liang
  • Phase-change memory and fabrication method thereof
    Patent number: 7569845
    Abstract: A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: August 4, 2009
    Assignees: Industrial Technology Research Institute, Powerchip Semiconductor Corp., Nanya Technology Corporation, ProMOS Technologies Inc., Winbond Electronics Corp.
    Inventors: Yi-Chan Chen, Wen-Han Wang