Patents by Inventor Wen Wu

Wen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098468
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Application
    Filed: January 29, 2020
    Publication date: April 1, 2021
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Publication number: 20210098397
    Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Chen-Hua Yu, Ming-Che Ho, Hung-Jui Kuo, Yi-Wen Wu, Tzung-Hui Lee
  • Patent number: 10965264
    Abstract: A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 30, 2021
    Assignee: Rafael Microelectronics, Inc.
    Inventors: Chih-Wen Wu, Po Chang Lin, Chun Hua Tseng
  • Patent number: 10955190
    Abstract: The present invention provides an exchangeable-battery photocuring device, comprising a supporting frame, having a plurality of walls, wherein the plurality of walls constitutes a chamber having at least one opening; a UV LED module, disposed on the supporting frame; a outer housing, having an external opening corresponding to the opening of the supporting frame; a control module; an exchangeable battery module, disposed on the supporting frame, wherein the exchangeable battery module comprises a battery holder and a battery, and the exchangeable battery module is electrically connected to the control module, and a handle. The present invention applying an exchangeable battery module achieves that the photocuring device is used without being constrained by location and space. Furthermore, the present invention also provides an exchangeable-battery photocuring device with a slidable lid and a portable battery photocuring device with a slidable lid.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: March 23, 2021
    Assignee: COSMEX CO. LTD.
    Inventors: Wan Chieh Hsieh, Ya Wen Wu, Wen Shan Chung, Yu Ching Li
  • Patent number: 10950495
    Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chih-Yuan Ting, Ya-Lien Lee, Chung-Wen Wu, Jeng-Shiou Chen
  • Publication number: 20210074636
    Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Inventors: Chih-Yuan Ting, Chung-Wen Wu
  • Patent number: 10943818
    Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chung-Ting Ko, Jr-Hung Li, Chi On Chui
  • Patent number: 10930564
    Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu, Peng Wang
  • Patent number: 10930586
    Abstract: An integrated fan-out package includes a die, an insulating encapsulation, a redistribution circuit structure, conductive terminals, and barrier layers. The insulating encapsulation encapsulates the die. The redistribution circuit structure includes a first redistribution conductive layer on the insulating encapsulation, a first inter-dielectric layer covering the first redistribution conductive layer, and a second redistribution conductive layer on the first inter-dielectric layer. The first redistribution conductive layer includes conductive through vias extending from a first surface of the insulating encapsulation to a second surface of the insulating encapsulation. The first inter-dielectric layer includes contact openings, portions of the second redistribution conductive layer filled in the contact openings are in contact with the first redistribution conductive layer and offset from the conductive through vias.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Wen Wu, Hung-Jui Kuo, Ming-Che Ho
  • Publication number: 20210050295
    Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.
    Type: Application
    Filed: March 6, 2020
    Publication date: February 18, 2021
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong
  • Publication number: 20210045259
    Abstract: A lock assembly comprising a base formed from a magnetic flux conducting material, the base secure to a chassis. A pin slidably disposed in the base and configured to move from a first open position to a second closed position. A magnet, disposed on a surface of a riser and configured to create a force on the pin that causes the pin to move from the open position to the closed position when the riser is disposed with the chassis.
    Type: Application
    Filed: August 5, 2019
    Publication date: February 11, 2021
    Applicant: DELL PRODUCTS L.P.
    Inventors: Hung-Wen Wu, Kuang Hsi Lin
  • Publication number: 20210040774
    Abstract: An equipment assembly is disclosed that includes a first equipment housing having a first penetration, a latch assembly disposed within the first equipment housing, a second equipment housing having a second penetration and a security bezel configured to cause the latch assembly to rotate through the first penetration and the second penetration.
    Type: Application
    Filed: August 5, 2019
    Publication date: February 11, 2021
    Applicant: DELL PRODUCTS L.P.
    Inventors: Alan Yl Wang, Hung-Wen Wu
  • Patent number: 10903797
    Abstract: A bias circuit for supplying a bias current to an RF power amplifier by using a field-effect transistor (FET) that is controlled by a logic control signal, such as a CMOS logic control signal, for turning on or turning off the bias current supplied to the RF power amplifier, wherein the bias current will be supplied to the RF power amplifier when the FET is on, and the bias current will not be supplied to the RF power amplifier when the FET is off.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: January 26, 2021
    Assignee: Rafael Microelectronics, Inc.
    Inventors: Chih-Wen Wu, Szu-Yao Chu
  • Publication number: 20210001457
    Abstract: The present application relates to the field of cutting technology, specifically, to a cutting platform and cutting equipment. The cutting platform may include a first bonding surface, a second bonding surface, and a cutting groove. The second bonding surface is opposite to the first bonding surface, and is used for bonding with a piece to be cut. The cutting groove penetrates the first bonding surface and the second bonding surface, and corresponds to the cutting path of a cutting device, and the cutting groove includes a first groove wall surface and second groove wall surface opposite to each other. A distance between the first groove wall surface and the second groove wall surface increases in a direction from the second bonding surface to the first bonding surface. The solution of the present application can improve product quality and equipment production efficiency.
    Type: Application
    Filed: June 23, 2020
    Publication date: January 7, 2021
    Inventors: Liangchao WANG, Wen WU, Jian ZHOU, Zengchao GONG, Yang WANG, Yang XIA
  • Patent number: 10884324
    Abstract: The disclosure provides a moving apparatus for a projector. The projector includes a body, a processing unit and a projection lens. The moving apparatus includes a base having a through-base opening. At least one moving stage movably disposed on a front side surface of the base along a plane and has at least one through-stage opening aligned with the through-base opening. At least one magnetic component disposed on a carrier board, wherein a projection position of the projection lens is positioned by the at least one magnetic board through magnetic attraction. The at least one magnetic component is electrically connected to the processing unit.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 5, 2021
    Assignee: Coretronic Corporation
    Inventors: Chih-Wen Wu, Chien-Tsai Chueh
  • Patent number: 10883082
    Abstract: The present invention includes methods for effecting phenotype conversion in a cell by transfecting the cell with phenotype-converting nucleic acid. Expression of the nucleic acids results in a phenotype conversion in the transfected cell. Preferably the phenotype-converting nucleic acid is a transcriptome, and more preferably an mRNA transcriptome.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: January 5, 2021
    Assignee: THE TRUSTEES OF THE UNIVERSITY OF PENNSYLVANIA
    Inventors: James Eberwine, Jai-Yoon Sul, Chia-Wen Wu, Fanyi Zeng, Junhyong Kim
  • Publication number: 20200411444
    Abstract: A package structure and a formation method of a package structure are provided. The method includes placing a semiconductor die over a redistribution structure and placing a conductive feature over the redistribution structure. The conductive feature has a support element and a solder element. The solder element extends along surfaces of the support element. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across the semiconductor die. The method further includes forming a protective layer to surround the conductive feature and the semiconductor die.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventors: Po-Hao TSAI, Techi WONG, Yi-Wen WU, Po-Yao CHUANG, Shin-Puu JENG
  • Patent number: 10880122
    Abstract: A method of forwarding a packet and a network device are provided. According to an example of the method, when serving as a previous-hop device of a destination device of a first tunnel, the network device receives a first notification message from the destination device of the first tunnel, where information relating the first tunnel is carried in the first notification message. The network device configures a forwarding entry, where a match domain of the forwarding entry includes the information relating the first tunnel. After an encapsulated data packet is received, and if the encapsulated data packet matches the forwarding entry, the network device decapsulates the encapsulated data packet and then forwards the decapsulated data packet to the destination device of the first tunnel.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 29, 2020
    Assignee: New H3C Technologies Co., Ltd.
    Inventors: Wen Wu, Liang Wang, Yuelei Chao
  • Patent number: 10877862
    Abstract: Provided is a method, system, and computer program product for managing requests received by a storage system. The method may include detecting, by one or more processors, a failure in a first storage system in response to a request to access data in the first storage system. The first storage system may include a primary storage for storing the data. A second storage system may be activated in response to the detected failure. The second storage system may include a first storage and a second storage. The first storage may include data synchronized with the primary storage of the first storage system. The second storage may be used to store data that corresponds to the request. The request may be managed using the second storage system.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yi Zhi Gao, Li Hui Guo, Long Wen Lan, Wen Wu Na, Yao Zhou
  • Publication number: 20200402868
    Abstract: A bottom emission microLED display includes a microLED disposed above a transparent substrate; a light guiding layer surrounding the microLED to controllably guide light generated by the microLED towards the transparent substrate; and a reflecting layer formed over the light guiding layer to reflect the light generated by the microLED downwards and to confine the light generated by the microLED to prevent the light from leaking upwards or sidewards.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Inventors: Biing-Seng Wu, Chao-Wen Wu