Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.

Abstract: A method includes forming an epitaxial source/drain (S/D) feature over a semiconductor layer, where the epitaxial S/D feature includes silicon (Si) and germanium (Ge), forming a trench to expose a portion of the epitaxial S/D feature, annealing the exposed portion of the epitaxial S/D feature, where the annealing forms at a top surface of the epitaxial S/D feature a first region having a first Ge concentration and a second region disposed below the first region having a second Ge concentration that is less than the first Ge concentration, oxidizing the first region, removing the oxidized first region, and forming an S/D contact in the trench over the second region.

Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Abstract: A method of transmitting a BGP message and a routing device are provided. According to an example of the method, a queue for holding BGP messages to be transmitted is partitioned into more than two subqueues according to types of BGP routes, where each of the subqueues is used to hold a BGP message carrying a corresponding type of BGP route. A BGP message carrying a BGP route to be advertised is placed into one of the more than two subqueues according to the type of the BGP route. A target subqueue is selected from the more than two subqueues according to a first scheduling algorithm, and a BGP message in the target subqueue is transmitted.

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

Abstract: A method to align a next generation sequencing read to a reference sequence includes: (a) receiving a sequencing read; (b) performing a first alignment of the sequencing read to a reference sequence so as to identify a target sequence within the reference sequence whereto the sequencing read maps; (c) selecting a first and a second anchor sequence; (d) attaching the first anchor sequence to the upstream region of the sequencing read and the second anchor sequence to the downstream region of the sequencing read so as to generate an extended sequencing read; (e) attaching the first anchor sequence to the upstream region of the target sequence and the second anchor sequence to the downstream region of the target sequence, so as to generate an extended target sequence; (f) performing a second alignment of the extended sequencing read to the extended target sequence, so that the second alignment is more correctly mapped to the target sequence than the first alignment; (g) identifying a position where one or more b

Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: A mold chase is provided, including a lower mold support and an upper mold support which are configured to be pressed together to form a mold cavity therebetween for receiving a wafer level substrate. The mold chase also includes multiple gates and at least one vent disposed along the periphery of the mold cavity. The gates are configured to allow a mold material to be injected into the mold cavity, and the vents are configured to release gas from the mold cavity. The distance between one of the gates and the closest vent is less than the diameter of the mold cavity.

Abstract: A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Abstract: A bottom emission microLED display includes a microLED disposed above a transparent substrate; a light guiding layer surrounding the microLED to controllably guide light generated by the microLED towards the transparent substrate; and a reflecting layer formed over the light guiding layer to reflect the light generated by the microLED downwards and to confine the light generated by the microLED to prevent the light from leaking upwards or sidewards.

Abstract: A real-time communication system includes a cloud server, multiple user devices having respective real-time communication software for communicating with the cloud server, and multiple dynamic expression rendering devices one-to-one communicating with the user devices respectively. A transmitting user device encodes and transmits a transmitter data, a receiver data and a dynamic expression ID of a selected dynamic expression. The cloud server decodes and transmits the transmitter data, the receiver data and the dynamic expression ID of the selected dynamic expression to a receiver user device. Based on the received dynamic expression ID, the real-time communication software of the receiver user device finds the dynamic expression.

Abstract: A bias circuit generates a bias current to an RF power amplifier used for transmitting RF signals, and the amount of the bias current supplied to the RF power amplifier can be configured in multiple modes through transistor switches that are controlled by mode control signals, so that the bias current supplied to the RF power amplifier can be adjusted according to the required power level of the transmitting RF signals. In addition, the bias current can be turned off by another transistor switch that is controlled by a power control signal for saving power while the RF power amplifier is not transmitting RF signals.

Abstract: Barcode tag conditions on sample tubes are detected utilizing side view images of sample tubes for streamlining handling in clinical laboratory automation systems. The condition of the tags may be classified into classes, each divided into a list of additional subcategories that cover individual characteristics of the tag quality. According to an embodiment, a tube characterization station (TCS) is utilized to obtain the side view images. The TCS enables the simultaneous or near-simultaneous collection of three images for each tube, resulting in a 360 degree side view for each tube. The method is based on a supervised scene understanding concept, resulting in an explanation of each pixel into its semantic meaning. Two parallel low-level cues for condition recognition, in combination with a tube model extraction cue, may be utilized. The semantic scene information is then integrated into a mid-level representation for final decision making into one of the condition classes.

Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.

Abstract: A vacuum transfer device includes a semiconductor substrate, which has a first hole disposed in a top portion of the semiconductor substrate; a nozzle disposed in a bottom portion of the semiconductor substrate and protruding downward, the nozzle being aligned with the first hole; and a second hole disposed through the nozzle and in the semiconductor substrate to meet the first hole.

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Abstract: A method of transmitting a BGP message and a routing device are provided. According to an example of the method, a queue for holding BGP messages to be transmitted is partitioned into more than two subqueues according to types of BGP routes, where each of the subqueues is used to hold a BGP message carrying a corresponding type of BGP route. A BGP message carrying a BGP route to be advertised is placed into one of the more than two subqueues according to the type of the BGP route. A target subqueue is selected from the more than two subqueues according to a first scheduling algorithm, and a BGP message in the target subqueue is transmitted.

Abstract: The present invention includes methods for effecting phenotype conversion in a cell by transfecting the cell with phenotype-converting nucleic acid. Expression of the nucleic acids results in a phenotype conversion in the transfected cell. Preferably the phenotype-converting nucleic acid is a transcriptome, and more preferably an mRNA transcriptome.

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first dielectric layer, a first conductive pattern and a barrier layer. The first conductive pattern is disposed in a second dielectric layer over the first dielectric layer. The barrier layer is disposed at an interface between the first conductive pattern and the second dielectric layer and an interface between the first dielectric layer and the second dielectric layer.