Patents by Inventor Wen Yi

Wen Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8936480
    Abstract: An electrical connector includes an insulative housing, a plurality of contacts and an actuator. The insulative housing defines a front opening and a back receiving space. The receiving space defines a horizontal plane and a vertical plane connecting each other. The contacts include retaining portions, contacting portions and pressing portions. Each contacting portion and corresponding pressing portion extends oppositely from the retained portion. The actuator includes a base portion and several separate costal parts extending from the base portion. Adjacent costal parts are connected by a shaft and the pressing portions are against to the shaft. The actuator rotates around the shaft and defines a cambered surface at the costal parts, the cambered surface slides between the horizontal plane and the vertical plane.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 20, 2015
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Wen-Yi Hsieh
  • Patent number: 8937369
    Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Yu-Shu Lin, Jei-Ming Chen, Wen-Yi Teng
  • Patent number: 8928531
    Abstract: An antenna module is provided. The antenna module includes a radiator, a feed conductor, a ground element, a ground conductor and a short conductor. The feed conductor is connected to the radiator. The ground conductor connects the radiator to the ground element. The short conductor connects the feed conductor to the ground conductor.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: January 6, 2015
    Assignee: Wistron Corp.
    Inventors: Pei-Cheng Hu, Kuo-Chang Su, Wen-Yi Tsai
  • Patent number: 8927388
    Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Jei-Ming Chen, Wen-Yi Teng, Chia-Lung Chang, Chih-Chien Liu
  • Patent number: 8926194
    Abstract: An optical board (100) includes a base layer (1), an optical module (4) assembled to the base layer, and an optical layer (2) attached to the base layer and defining a receiving recess (23). The optical module includes a ferrule (41) received in the receiving recess and defining a number of grooves (4131), and a number of optical circuits (42) positioned in the grooves of the ferrule. The optical circuits extend outside of the ferrule and into the optical layer.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: January 6, 2015
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Yen-Chih Chang, Wen-Yi Hsieh, Ke-Hao Chen
  • Patent number: 8921238
    Abstract: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen
  • Patent number: 8916032
    Abstract: The present invention discloses an improved method of LED reflector manufacturing process where the method includes providing a substrate, wherein said substrate comprises a reflector unit, and a Light Emitting Diode; providing a shield member with ferromagnetic property; placing said shield member over the desired area of over the substrate; providing a magnet where said shield member is attracted to; placing said magnet immediately below the substrate wherein said magnet is capable of immobilizing the shield member over the substrate; performing a vacuum deposition coating; and removing the magnet and the shield member.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: December 23, 2014
    Inventors: Roger Wen Yi Hsu, Shu-Yu Hsu, Shu-His Hsu
  • Patent number: 8917114
    Abstract: A voltage detection circuit including a comparator circuit, a tunable gain circuit and a switch circuit is disclosed. The comparator circuit has a first input terminal and a second input terminal. The tunable gain circuit is coupled between the first input terminal and a reference signal. The tunable gain circuit has a plurality of gain configurations. The tunable gain circuit adjusts the reference signal and transmits the adjusted reference signal to the first input terminal. The switch circuit selectively transmits a signal under test or the reference signal to the second input terminal. When the voltage detection circuit is in an auto-trimming mode, the switch circuit transmits the reference signal to the second input terminal and the tunable gain circuit sequentially adopts the gain configurations until the comparator circuit detects that voltage levels of the first input terminal and the second input terminal are substantially equal.
    Type: Grant
    Filed: November 20, 2011
    Date of Patent: December 23, 2014
    Assignee: Nuvoton Technology Corporation
    Inventor: Wen-Yi Li
  • Publication number: 20140368638
    Abstract: The present invention provides a method of mobile image identification for flow velocity and the apparatus thereof. The present invention integrates laser-light module and mobile photographing devices such as smartphones, cameras, or tablet computers. After multiple laser spots are projected on the surface of flowing water, water-surface images including the laser spots are photographed continuously. Then the software program of image identification in the mobile photographing device performs calculations and coordinate conversion. According to the difference between multiple water-surface images taken continuously, the flow-velocity information of the water surface is given.
    Type: Application
    Filed: June 18, 2014
    Publication date: December 18, 2014
    Inventors: FRANCO LIN, WEN-YI CHANG, LUNG-CHENG LEE, HUNG-TA HSIAO, WHEY-FONE TSAI, TAI-SHAN LIAO, SHUN-CHUNG TSUNG, JIHN-SUNG LAI, CHIN-HSIUNG LOH, SHIH-CHUNG KANG, YAO-YU YANG
  • Patent number: 8908195
    Abstract: The present invention relates to a method for measuring cracks remotely and the device thereof. First, multiple laser spots with known a shape are projected onto a remote wall and beside a crack. Then, by using geometric calculations, the relative coordinates of the laser spots on the wall and the real distance can be given and used as the reference length of the crack. Next, a camera is used for taking a picture of the remote crack along with the laser spots; the image identification technology is used for calculating the relevant parameters of the crack. Thereby, to acquire the parameters of the crack, a user needs not to be present at the site for measuring at a short distance or placing a reference object, and thus providing safety and convenience.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 9, 2014
    Assignee: National Applied Research Laboratories
    Inventors: Wen-Yi Chang, Franco Lin, Lung-Cheng Lee, Hung-Ta Hsiao, Shou-I Chen, Yu-Chi Sung, Tai-Shan Liao, Chih-Yen Chen
  • Patent number: 8901732
    Abstract: Various packages and methods are disclosed. A package according to an embodiment includes a substrate, a chip attached to a surface of the substrate with electrical connectors, a molding compound on the surface of the substrate and around the chip, an adhesive on a surface of the chip that is distal from the surface of the substrate, and a lid on the adhesive. In an embodiment, a region between the molding compound and the lid at a corner of the lid is free from the adhesive. In another embodiment, the lid has a recess in a surface of the lid facing the surface of the molding compound.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chih Yew, Fu-Jen Li, Wen-Yi Lin, Po-Yao Lin, Kuo-Chuan Liu
  • Publication number: 20140347771
    Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base region of semiconductor material having a first conductivity type, a second base region of semiconductor material having the first conductivity type and a dopant concentration that is less than the first base region, a third base region of semiconductor material having the first conductivity type and a dopant concentration that is greater than the second base region, an emitter region of semiconductor material having a second conductivity type opposite the first conductivity type within the first base region, and a collector region of semiconductor material having the second conductivity type. At least a portion of the second base region resides between the third base region and the first base region and at least a portion of the first base region resides between the emitter region and the collector region.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Inventors: Rouying ZHAN, Chai Ean GILL, Wen-Yi CHEN, Michael H. KANESHIRO
  • Publication number: 20140346560
    Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base well region having a first conductivity type, an emitter region within the base well region having a second conductivity type opposite the first conductivity type, a collector region having the second conductivity type, a first floating region having the second conductivity type within the base well region between the emitter region and the collector region, and a second floating region having the first conductivity type within the base well region between the first floating region and the collector region. The floating regions within the base well region are electrically connected to reduce current gain and improve holding voltage.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Inventors: Rouying ZHAN, Chai Ean GILL, Wen-Yi CHEN, Michael H. KANESHIRO
  • Patent number: 8895435
    Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Publication number: 20140340625
    Abstract: A display panel, including a device substrate, an opposite substrate, a sealant, and a display medium, is provided. A pixel array of the device substrate is located in a display region, and a periphery circuit of the device substrate is located in a non-display region, wherein the periphery circuit includes at least one driving device, a planarization layer, and at least one wire. The planarization layer covers the driving device. The wire is located on the planarization layer, and the wire is electrically connected with the driving device and disposed to overlap the driving device. The opposite substrate is located opposite to the device substrate, and the sealant is located in the non-display region therebetween and covers the wire. The display medium is located between the device substrate, the opposite substrate, and the sealant. A manufacturing method of a display panel is also provided.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 20, 2014
    Applicant: Au Optronics Corporation
    Inventors: Wen-Yi Hsu, Maw-Song Chen
  • Publication number: 20140340999
    Abstract: A medication reminder method and system are provided. A carrier device acquires medication information of a medication from a medication information server via a network. The medication information includes a pre-determined time interval prescribed for the medication. The carrier device activates an alarm device to emit an alarm signal to remind a user to take the medication on expiry of the pre-determined time interval.
    Type: Application
    Filed: November 21, 2013
    Publication date: November 20, 2014
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YA-BEI ZHANG, WEN-YI WU
  • Publication number: 20140332361
    Abstract: A touch inductive unit includes a receiving electrode pattern and a driving electrode pattern. The receiving electrode pattern includes a first main stem, a first branch portion and a second branch portion. The first branch portion and the second branch portion are extended from the first main stem. The driving electrode pattern includes a second main stem, a third branch portion and a fourth branch portion. The third branch portion and the fourth branch portion are extended from the second main stem. The receiving electrode pattern and the driving electrode pattern are interdigitated and physically spaced apart from each other.
    Type: Application
    Filed: May 12, 2014
    Publication date: November 13, 2014
    Applicant: WINTEK CORPORATION
    Inventors: Chi-Ming Huang, Shyh-Jeng Chen, Pei-Fang Tsai, Ming-Chuan Lin, Hsueh-Chih Wu, Wen-Hung Wang, Wen-Yi Wang
  • Publication number: 20140323699
    Abstract: The present invention provides a method for labeling or detecting a protein with certain glycosyl groups. The methods are particularly useful for detecting cancer cells comprising the detected glycosyl groups. The present invention further provides labeling agents and detection agents, labeled proteins and mixtures, and kits and arrays thereof.
    Type: Application
    Filed: January 3, 2014
    Publication date: October 30, 2014
    Applicant: California Institute of Technology
    Inventors: Linda C. Hsieh-Wilson, Wen Yi, Jean-Luc Chaubard
  • Patent number: 8847369
    Abstract: Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chih Yew, Wen-Yi Lin, Jiun Yi Wu, Po-Yao Lin
  • Patent number: D714256
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: September 30, 2014
    Assignee: Compal Electronics, Inc.
    Inventors: Hui-Jou Tsai, Yung-Hsiang Chen, Wen-Yi Chiu, Kuan-Yu Chou, Hsing-Yi Kao, Hsiang-Ling Liu