Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.

Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

Abstract: A protection device including a first housing, a second housing, a power component, a protective cover and a circuit board is provided. The second housing and the first housing are assembled to each other to define an internal space. The power component is disposed on the second housing and located in the internal space. The protective cover covers the power component and is located in the internal space. The circuit board is disposed in the internal space, and the protective cover is located between the circuit board and the power component. At least one pin of the power component protrudes beyond the circuit board through the protective cover and the circuit board.

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.

Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

Abstract: An MRAM structure includes a dielectric layer. A contact hole is disposed in the dielectric layer. A contact plug fills in the contact hole and protrudes out of the dielectric layer. The contact plug includes a lower portion and an upper portion. The lower portion fills in the contact hole. The upper portion is outside of the contact hole. The upper portion has a top side and a bottom side greater than the top side. The top side and the bottom side are parallel. The bottom side is closer to the contact hole than the top side. An MRAM is disposed on the contact hole and contacts the contact plug.

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

Abstract: Systems and methods are provided for controlling two or more PSUs of a server system. An exemplary method comprises first determining whether the PSUs are switched on to an AC power source. If the PSUs are found not switched on to an AC power source, the method further comprises restarting the AC power source for the PSUs and completing a software-based recovery process. If the PSUs are found to be switched on to an AC power source, the method further comprises determining whether the PSUs meet a predefined criterion. If the PSUs do meet a predefined criterion, the method further comprises disabling a cold-redundancy mode for the PSUs. If the PSUs do not meet a predefined criterion, the method further comprises starting a wake-up process for a first PSU from a cold-redundancy mode.

Abstract: Semiconductor structure and fabrication method are provided. The method includes: providing a substrate including device regions and isolation regions, adjacent with one another; providing discrete fins on the substrate, pitches between adjacent fins being substantially same; forming a protective layer on the sidewalls of the fins; removing a partial thickness of the fins in the isolation regions along with a partial thickness of the protective layer in the isolation regions by a first etching process; forming dummy fins by a second etching process to etch the remaining fins in the isolation regions using the remaining protective layers as a mask; removing the remaining protective layer after the second etching process; and forming isolation structures in the isolation regions on the substrate. The isolation structures have a top lower than the fins in the device regions and higher than the dummy fins in the isolation regions.

Abstract: A system for testing a data storage device includes the data storage device, an electronic device and a computer device. The electronic device includes a host device coupled to the data storage device and communicating with the data storage device via an interface logic. The computer device is coupled to the electronic device and is configured to issue a plurality of commands to test the data storage device in a test procedure. When the electronic device has been successfully started up, the computer device issues a first command to the electronic device to trigger the electronic device to enter a hibernate mode. After waiting for a first predetermined period of time, the computer device issues a second command to the electronic device, so as to wake up the electronic device.

Abstract: A Sigma-Delta (?-?) analog-to-digital converter (ADC) and operation method thereof are provided. The ?-? ADC includes a ?-? modulator, a dynamic element matching (DEM) circuit and a control circuit. An input terminal of the ?-? modulator is configured to receive an analog signal. The ?-? modulator is configured to convert the analog signal into a digital signal based on a feedback signal. The DEM circuit is coupled to the ?-? modulator to receive the digital signal. The DEM circuit is configured to perform a DEM algorithm on the digital signal to generate a feedback signal, and provide the feedback signal to the ?-? modulator. The control circuit listens to the digital signal to detect a mute period. The control circuit disables the DEM circuit during the mute period to suspend a progress of the DEM algorithm.

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer; forming a cap layer on the bottom electrode layer; and removing part of the cap layer, part of the bottom electrode layer, and part of the IMD layer to form a trench.

Abstract: An overlay compensation method and a related system are presented. The method includes: acquiring a first offset vector reflecting the relative position between overlay marks of a middle and a bottom target layers; acquiring a second offset vector reflecting the relative position between the overlay marks of a top and the middle target layers; decomposing the first offset vector into a first compensable component and a first uncompensable component; decomposing the second offset vector into a second compensable component and a second uncompensable component; computing minimum values of the first uncompensable component and the second uncompensable component; computing optimized values for the first compensable component and the second compensable component; and computing a third compensable component of a third offset vector reflecting the relative position between the overlay marks of the top and the bottom target layers.

Abstract: A method for performing memory access management with aid of machine learning in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: in the memory device, during a training phase, performing machine learning according to a predetermined database regarding threshold voltage distribution, to generate at least one threshold voltage identification model, wherein the at least one threshold voltage identification model is utilized for determining bit information read from a memory cell of the NV memory; and in the memory device, during an identification phase, obtaining representative information of one or more reference voltages when reading the NV memory, for performing machine identification according to the at least one threshold voltage identification model to generate read data, wherein the read data includes the bit information.