Abstract: An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.

Abstract: The present invention in various embodiments relates to a variety of different types of fluidic adaptive lens systems, pumping systems for implementation in such lens systems, other systems employing such lens systems, and related methods of fabrication. In at least some embodiments, the present invention relates to a lens system that includes a reservoir having at least one flexible wall, a first actuator coupled in relation to the reservoir, and a terminal at which is located at least one of an integrated fluidic lens and a port configured to be coupled to an external fluidic lens. The terminal is coupled to at least one of the reservoir and the actuator, and at least one of the actuator and a first pumping system including the actuator is capable of causing fluid to be moved at least one of from the reservoir toward the terminal, and from the terminal toward the reservoir.

Abstract: Provided is a method of making microarrays that includes providing a substrate with discrete first microfeatures that have a first profile, and depositing vapor-coated materials onto the first microfeatures to form second microfeatures having a second profile that is substantially different from the first profile. Also provided is a method of adding a replication material to the vapor-coated microfeatures to form a mold. Microarrays made by this method can be used as substrates for surface-enhanced Raman spectroscopy (SERS).

Abstract: A method of making a microresonator device includes the steps of providing at least a first substrate and providing a waveguide integrated on the substrate. The waveguide includes a core and a metal cladding layer on at least part of one boundary of the core. Another step is positioning a microresonator so that it is in an optically coupling relationship with the waveguide.

Abstract: Provided is a method of making hierarchical structures that contain nanofeatures and microstructures. The method includes adding the nanofeatures to existing microstructures using nanoparticles as an etch mask.

Abstract: A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation.

Abstract: A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material.

Abstract: A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.

Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Abstract: A silicone mold comprising and oxidized, patterned surface and a layer of perfluoroether silane release agent is described. The mold enables 2nd generation silicone molds to be replicated, i.e. silicone molds from silicone molds.

Abstract: A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.

Abstract: A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

Abstract: A method for fabricating a microelectronic structure provides for forming a backfilling material layer at least laterally adjacent, and preferably laterally adjoining, a resist layer located over a substrate. Preferably, the resist layer comprises a surface treated resist layer. Optionally, the backfilling material layer may be surface treated similarly to the surface treated resist layer. Under such circumstances: (1) surface portions of the backfilling material layer and resist layer; and (2) remaining portions of the backfilling material layer and resist layer, may be sequentially stripped using a two step etch method, such as a two step plasma etch method. Alternatively, a surface portion of the surface treated resist layer only may be stripped while using a first etch method, and the remaining portions of the resist layer and backfilling material layer may be planarized prior to being simultaneously stripped while using a second etch method.

Abstract: A system that optimizes packet transmissions during a convergecast operation in a convergecast network. During operation, the system receives a request to perform the convergecast operation in the convergecast network. In response to the request, the system constructs a convergecast-tree, which includes the base-station and the plurality of nodes, based on hop counts from the plurality of nodes to the base-station. Next, the system linearizes the convergecast-tree so that the convergecast-tree contains a plurality of linear branches. The system then schedules packet transmission for each of the linear branches and each node in each branch based on a set of predetermined criteria to obtain a scheduled order. Finally, the system performs packet transmissions in the convergecast-tree using the scheduled order. Note that performing the convergecast operation in this way substantially optimizes the convergecast operation by reducing a total number of timeslots required to complete the convergecast operation.

Abstract: A CMOS structure is disclosed in which both type of FET devices have gate insulators containing high-k dielectrics, and gates containing metals. The threshold of the two type of devices are adjusted in separate manners. One type of device has its threshold set by exposing the high-k dielectric to oxygen. During the oxygen exposure the other type of device is covered by a stressing dielectric layer, which layer also prevents oxygen penetration to its high-k gate dielectric. The high performance of the CMOS structure is further enhanced by adjusting the effective workfunctions of the gates to near band-edge values both NFET and PFET devices.

Abstract: Provided is a method of fabricating hierarchical articles that contain nanofeatures and microstructures. The method includes providing a substrate that includes nanofeatures and then creating microstructures adding a layer, removing at least a portion of the layer to reveal at least a portion of the substrate.

Abstract: A method is presented for a time-aware strategy utilized within message-initiated constraint-based routing for digital message communication among nodes in an ad-hoc network, in which each node includes attributes. The method includes determining local attributes for each of the nodes and defining constraints on the attributes. Each node is provided access to the attributes of each neighboring node, with a neighboring node being a node that is one hop away. Each message transmitted over the network has a message type, which includes a destination specification, route specification, and objective specification. Constraint checking and cost estimation checking are performed for each message type.

Abstract: A multifunctional optical film for enhancing light extraction includes a flexible substrate, a structured layer, and a backfill layer. The structured layer effectively uses microreplicated diffractive or scattering nanostructures located near enough to the light generation region to enable extraction of an evanescent wave from an organic light emitting diode (OLED) device. The backfill layer has a material having an index of refraction different from the index of refraction of the structured layer. The backfill layer also provides a planarizing layer over the structured layer in order to conform the light extraction film to a layer of an OLED lighting device such as solid state lighting devices or backlight units. The film may have additional layers added to or incorporated within it to an emissive surface in order to effect additional functionalities beyond improvement of light extraction efficiency.

Abstract: A multifunctional optical film for enhancing light extraction includes a flexible substrate, a structured layer, and a backfill layer. The structured layer effectively uses microreplicated diffractive or scattering nanostructures located near enough to the light generation region to enable extraction of an evanescent wave from an organic light emitting diode (OLED) device. The backfill layer has a material having an index of refraction different from the index of refraction of the structured layer. The backfill layer also provides a planarizing layer over the structured layer in order to conform the light extraction film to a layer of an OLED display device. The film may have additional layers added to or incorporated within it to an emissive surface in order to effect additional functionalities beyond improvement of light extraction efficiency.

Abstract: A network routing method and system may include initializing the network by determining, for each node of the network, a number of hops to a root node and delaying forwarding to the root node, for each node, a packet received, wherein the delay in forwarding the packet received to the root node from a forwarding node depends upon the number of hops separating the root node from the forwarding node. A network routing method and system may include initializing the network by determining, for each node of the network, a number of hops to a root node, determining, for a forwarding node that receives a packet from a sending node, whether to forward the packet to a root node, determining a delay after which the packet is to be forwarded to the root node and determining a probability of forwarding the packet to the root node.