Patents by Inventor Yong Lim

Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110042760
    Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.
    Type: Application
    Filed: August 23, 2010
    Publication date: February 24, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Hong-Seon YANG, Heung-Jae CHO, Yong-Soo KIM, Kwan-Yong LIM
  • Publication number: 20110038280
    Abstract: Disclosed are user equipment and a base station in a carrier aggregation system, and a call admission method thereof. The user equipment includes a plurality of physical layers, and the base station provides multiple component carriers. When messages for connection setup are transmitted and received between the user equipment and base station, the messages include information about what component carriers are selected by the physical layers, information about what component carriers are selectable by the physical layers, and information about calculations for uplink timing alignment, and call admission control and load balancing is performed based on the information included in the messages. Accordingly, in the carrier aggregation system, quicker call admission and load balancing are achieved.
    Type: Application
    Filed: October 30, 2009
    Publication date: February 17, 2011
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kwang-Ryul Jung, Soon-Yong Lim, Ae-Soon Park
  • Patent number: 7838364
    Abstract: A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yong-Soo Kim, Hong-Seon Yang, Se-Aug Jang, Seung-Ho Pyi, Kwon Hong, Heung-Jae Cho, Kwan-Yong Lim, Min-Gyu Sung, Seung-Ryong Lee, Tae-Yoon Kim
  • Patent number: 7825014
    Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Hong-Seon Yang, Tae-Kwon Lee, Won Kim, Kwan-Yong Lim, Seung-Ryong Lee
  • Patent number: 7816909
    Abstract: Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: October 19, 2010
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd
    Inventors: Victor Chan, Khee Yong Lim
  • Patent number: 7813291
    Abstract: Disclosed is a method and device for requesting and reporting channel quality information in a mobile communication system. A base station a locates a dedicated feedback channel for channel quality information report to an uplink radio resource, transmits the allocation information to subscriber stations, and generates a CQI report message to request channel quality information from the subscriber stations. The subscriber stations receive the CQI report message from the base station, measures a radio channel quality for communication with the base station, generates channel quality information, generates a CQI response message including the channel quality information, and transmit—the CQI response message to the base station through a dedicates feedback channel designated in the allocation information.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: October 12, 2010
    Assignees: Electronics and Telecommunications Research Institute, Samsung Electronics Co., Ltd., KT Corporation, SK Telecom Co., Ltd., KTFreetel Co., Ltd, Hanaro Telecom, Inc.
    Inventors: Chul-Sik Yoon, Jae-Heung Kim, Kun-Min Yeo, Soon-Yong Lim, Byung-Han Ryu
  • Patent number: 7800197
    Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: September 21, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yun Taek Hwang, Kwang Yong Lim
  • Publication number: 20100225796
    Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.
    Type: Application
    Filed: December 7, 2009
    Publication date: September 9, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Lim, Kyoung-Min Koh, Kyung-Min Kim
  • Publication number: 20100219466
    Abstract: In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed.
    Type: Application
    Filed: May 7, 2010
    Publication date: September 2, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim, Se-Aug Jang
  • Patent number: 7781333
    Abstract: A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: August 24, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Hong-Seon Yang, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim
  • Publication number: 20100207798
    Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.
    Type: Application
    Filed: November 13, 2009
    Publication date: August 19, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong Lim, Kyoung-Min Koh, Kyung-Min Kim
  • Publication number: 20100208112
    Abstract: A ramp generator includes a row decoder, a column decoder, a current cell matrix and a current-voltage converter. The row decoder generates row selection signals, and the column decoder generates column selection signals. Each of current cells included in the current cell matrix is turned on to provide a unit current if a corresponding row selection signal and a corresponding column selection signal are activated. Each of the current cells is maintained to be turned on even if the corresponding row selection signal or the corresponding column selection signal is deactivated. The current cell matrix outputs an output current by summing unit currents provided from the current cells that are turned on. The current-voltage converter converts the output current of the current cell matrix into a ramp voltage. Therefore, the ramp generator may have a small size and prevent a glitch.
    Type: Application
    Filed: February 1, 2010
    Publication date: August 19, 2010
    Inventor: Yong Lim
  • Patent number: 7769414
    Abstract: Disclosed is a power saving mode control system (200) and method in a wireless portable Internet system. Stations in the sleep mode are grouped by aligning listening intervals of the stations which enter the sleep mode in the power saving management system wherein the sleep interval for receiving no traffic data is exponentially increased. Therefore, the sleep mode of the grouped subscriber stations are easily managed, and power saving efficiency is enhanced and system complexity is lowered by easily and quickly detecting data states provided to the corresponding stations.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: August 3, 2010
    Assignees: Electronics and Telecommunications Research Institute, KT Corporation, Samsung Electronics Co., Ltd., Hanaro Telecom, Inc., SK Telecom Co., Ltd.
    Inventors: Chul-Sik Yoon, Soon-Yong Lim, Jae-Heung Kim, Kun-Min Yeo, Byung-Han Ryu, Seung-Ku Hwang
  • Publication number: 20100181611
    Abstract: A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 22, 2010
    Inventors: Kwon Hong, Kwan-Yong Lim
  • Patent number: 7752519
    Abstract: Provided is a method for generating a feedback message for ARQ including recording an ACK type in a first field; estimating the last block sequence number of successively ACKed blocks and recording the estimated last block sequence number in a second field; recording the number of groups of successively ACKed blocks after the estimated last block sequence number as the number of ACK MAPs in a third field; recording the startblock sequence number of the respective ACK MAPs in a fourth field; recording the lengths of the respective ACK MAPs in a fifth field corresponding to the recorded start block sequence number; and sending a feedback message including information on the first to the fifth fields.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: July 6, 2010
    Assignees: Electronics and Telecommunications Research Institute, Samsung Electronics Co., Ltd., KT Corporation, SK Telecom Co., Ltd., KTFreetel Co., Ltd., Hanaro Telecom., Inc.
    Inventors: Kun-Min Yeo, Chul-Sik Yoon, Jae-Heung Kim, Soon-Yong Lim, Byung-Han Ryu
  • Publication number: 20100159822
    Abstract: Provided is an apparatus and method for providing a Multimedia Broadcast and Multicast Service (MBMS) in a wireless communication system, e.g., a 3rd-Generation Partnership Project (3GPP) Long-Term Evolution (LTE)-Advanced mobile communication system. The method for providing an MBMS in a mobile communication system includes: multiplexing MBMS traffic channels providing MBMS traffic data and an MBMS control channel proving control information of MBMS into a downlink-shared channel; processing and transmitting data of the downlink-shared channel to be transmitted through a physical downlink-shared channel of a physical channel; and generating and transmitting a physical downlink control channel which includes identifiers for indicating MBMS data and information to designate a receiving terminal of data transmitted through the physical downlink-shared channel.
    Type: Application
    Filed: September 8, 2009
    Publication date: June 24, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Soon-Yong LIM, Ae-Soon PARK
  • Patent number: 7741170
    Abstract: A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: June 22, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kwon Hong, Kwan-Yong Lim
  • Publication number: 20100150082
    Abstract: Provided is a buffer status reporting method of a terminal device in a mobile communication system. The buffer status reporting method includes obtaining a radio resource allocation for a plurality of component carriers from a base station, configuring a plurality of medium access control-protocol data units (MAC-PDUs) including buffer status information corresponding to the plurality of component carriers, the plurality of MAC-PDUs including generated sequence numbers (SNs), and transmitting the plurality of MAC-PDUs to the base station through the plurality of component carriers.
    Type: Application
    Filed: July 23, 2009
    Publication date: June 17, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jae Wook SHIN, Kwang Ryul Jung, Soon Yong Lim, Ae-soon Park
  • Publication number: 20100148042
    Abstract: A sensor for angle measurement of a joint is disclosed. The sensor comprises a code strip, a linear encoder configured to detect relative movement between the linear encoder and the code strip, and a microcontroller configured to compute angular rotation of the joint from linear displacement obtained by the relative movement. The relative movement corresponds to rotation of the joint. A corresponding method and system are also disclosed.
    Type: Application
    Filed: January 18, 2008
    Publication date: June 17, 2010
    Applicant: Nanyang Technological University
    Inventors: I-Ming Chen, Kwang Yong Lim, Young Koon Goh, Song Huat Yeo, Been-Lim Duh
  • Publication number: 20100133619
    Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.
    Type: Application
    Filed: February 2, 2010
    Publication date: June 3, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Se-Aug JANG, Heung-Jae CHO, Kwan-Yong LIM, Tae-Yoon KIM