Patents by Inventor Yong Lim

Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • WIRELESS COMMUNICATION SYSTEM WITH PROTOCOL ARCHITECTURE FOR IMPROVING LATENCY
    Publication number: 20100136987
    Abstract: The present invention relates to a wireless communication system having protocol architecture for reducing latency of a cellular system. In the protocol architecture of the wireless communication system in the cellular system, a physical layer supports wireless transmission of the cellular system and estimates a radio channel condition. A data link layer determines a data transmission mode based on a QoS of user data and the radio channel condition estimated by the physical layer and performs segmentation and assembly of the packet data, and a network layer establishes and releases a radio bearer for transmitting packet data transmitted from the data link layer and a control command. A control service access point is provided for control information transmission between the data link layer and the physical layer.
    Type: Application
    Filed: June 15, 2006
    Publication date: June 3, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kang-Hee Kim, Soo-Jung Jung, Geon-Min Yeo, Soon-Yong Lim, Kyung-Seok Lee, Jae-Heung Kim, Il-Soon Jang, Hyun-Hwa Seo, Jung-Im Kim, Mu-Yong Shin, Byung-Han Ryu
  • INTER-CARRIER MEMBER HANDOVER APPARATUS AND METHOD
    Publication number: 20100120431
    Abstract: Provided are an inter-carrier member handover apparatus and method. In the inter-carrier member handover apparatus and method, data is transmitted or received by allocating a plurality of carriers to a single mobile terminal, a carrier aggregation, which includes a plurality of carrier members that process the allocated carriers, is managed, and a handover between the carrier members in the managed carrier aggregation is processed when the handover is required. Therefore, an intra-base station handover can be performed when a mobile terminal and a base station exchange data using a plurality of carrier frequency bands.
    Type: Application
    Filed: September 18, 2009
    Publication date: May 13, 2010
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: You-sun HWANG, Soon-yong LIM, Ae-soon PARK
  • Semiconductor device with vertical channel transistor and method for fabricating the same
    Patent number: 7713823
    Abstract: In a high speed vertical channel transistor, a pillar structure is formed over a substrate, a gate electrode surrounds an outer wall of a lower portion of the pillar structure; and a word line extends in a direction to partially contact an outer wall of the gate electrode. The word line shifts toward a side of the pillar structure resulting in increased transistor speed.
    Type: Grant
    Filed: June 29, 2008
    Date of Patent: May 11, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Heung-Jae Cho, Yong-Soo Kim, Kwan-Yong Lim, Se-Aug Jang
  • SELF-POWERED IN-PIPE FLUID METER AND PIPING NETWORK COMPRISING A PLURALITY OF SUCH FLUID METERS
    Publication number: 20100085211
    Abstract: A self-powered in-pipe fluid meter to be mounted inside of a pipe carrying a fluid therein. The fluid meter comprises at least one sensing unit capable of measuring one or more parameters of the fluid inside of the pipe; a telemetric data transmission unit capable of telemetrically transmitting data including a measured fluid parameter to a host terminal and/or another fluid meter; and at least one fluid-driven power source unit capable of generating power from the fluid flow within the pipe and supplying power to the sensing unit and/or the transmission unit.
    Type: Application
    Filed: August 6, 2007
    Publication date: April 8, 2010
    Applicant: Agency for Science, Technology and Research
    Inventors: Zhenfeng Wang, Ser Yong Lim, Wei Fan, Danhong Zhang
  • DUAL POLYSILICON GATE OF A SEMICONDUCTOR DEVICE WITH A MULTI-PLANE CHANNEL
    Publication number: 20100084714
    Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.
    Type: Application
    Filed: December 7, 2009
    Publication date: April 8, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong LIM, Heung-Jae CHO, Min-Gyu SUNG
  • Method for fabricating semiconductor device
    Patent number: 7687389
    Abstract: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a first gate conductive layer over the gate insulation layer, forming a barrier metal over the first gate conductive layer, sequentially forming a second gate conductive layer and a gate hard mask over the barrier metal, patterning the gate hard mask, the second gate conductive layer, the barrier metal, the first gate conductive layer, and the gate insulation layer to form a gate pattern, and performing a plasma selective gate re-oxidation process on the gate pattern.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kwan-Yong Lim, Min-Gyu Sung, Heung-Jae Cho, Hong-Seon Yang
  • Semiconductor device having a fin transistor and method for fabricating the same
    Patent number: 7682911
    Abstract: A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: March 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se-Aug Jang, Heung-Jae Cho, Kwan-Yong Lim, Tae-Yoon Kim
  • APPARATUS AND METHOD FOR TIME-SHIFT SERVICE BASED ON MULTIMEDIA INFORMATION, APPARATUS FOR REPRODUCING MULTIMEDIA USING THE SAME
    Publication number: 20100070644
    Abstract: Provided are a time shift service apparatus and method based on multimedia information, and a multimedia reproducing apparatus using the same. The timeshift service apparatus includes: a timeshift buffering unit for storing a multimedia stream according a timeshift service requested from an outside device; a time obtaining unit for obtaining time information about times of starting and ending a timeshift service according to the timeshift service request; a memory managing unit for storing a multimedia stream, which is serviced based on the obtained time information by the time obtaining unit, in the timeshift buffering unit; and an information generating unit for generating detailed information for the multimedia stream stored in the timeshift buffering unit.
    Type: Application
    Filed: December 3, 2007
    Publication date: March 18, 2010
    Inventors: Seong-Yong Lim, Ji-Hoon Choi, Hyun-Cheol Kim, Joo-Myoung Seok, Han-Kyu Lee, Jin-Woo Hong
  • Spacer-less Low-K Dielectric Processes
    Publication number: 20100059831
    Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
    Type: Application
    Filed: November 6, 2009
    Publication date: March 11, 2010
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
  • Method for fabricating semiconductor device with interface barrier
    Patent number: 7666785
    Abstract: A method for fabricating a semiconductor memory device includes forming a first layer, injecting a tungsten source gas and a silicon source gas simultaneously to form a tungsten silicide layer over the first layer, forming a tungsten nitride layer over the tungsten silicide layer without a post purge process of additionally supplying the silicon source gas, and forming a second layer over the tungsten nitride layer.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Yong-Soo Kim, Kwan-Yong Lim
  • Non-volatile memory device with conductive sidewall spacer and method for fabricating the same
    Patent number: 7667253
    Abstract: The present invention relates to a non-volatile memory device having conductive sidewall spacers and a method for fabricating the same. The non-volatile memory device includes: a substrate; a gate insulation layer formed on the substrate; a gate structure formed on the gate insulation layer; a pair of sidewall spacers formed on sidewalls of the gate structure; a pair of conductive sidewall spacers for trapping/detrapping charges formed on the pair of sidewall spacers; a pair of lightly doped drain regions formed in the substrate disposed beneath the sidewalls of the gate structure; and a pair of source/drain regions formed in the substrate disposed beneath edge portions of the pair of conductive sidewall spacers.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: February 23, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Yong-Soo Kim, Se-Aug Jang, Hyun-Chul Sohn
  • Double Anneal with Improved Reliability for Dual Contact Etch Stop Liner Scheme
    Publication number: 20100041242
    Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.
    Type: Application
    Filed: October 19, 2009
    Publication date: February 18, 2010
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Khee Yong LIM, Victor CHAN, Eng Hua LIM, Wenhe LIN, Jamin F. FEN
  • Dynamic range extending method and apparatus using subsampling
    Publication number: 20100007778
    Abstract: A method and apparatus subsampling a plurality of signals from one frame of a pixel array, pixels within the pixel array belonging to one of at least two sets, each set configured to sense values of a same image parameter, includes controlling integration times for first and second signals for each set output from the pixel array, controlling including using a first integration time for the first signal of the set and using a second integration time, different than the first integration time, for the second signal of the set, and calculating a synthesized value for each set using the first and second signals having different integration times.
    Type: Application
    Filed: May 7, 2009
    Publication date: January 14, 2010
    Inventor: Yong Lim
  • Pseudo-digital average sub sampling method and apparatus
    Publication number: 20090309991
    Abstract: A method of k*k subsampling, where k is an integer greater than one, a full frame readout on a plurality of pixels arranged in rows and columns, each pixel belonging to one of at least two sets, a first set configured to sense a first value of an image parameter and a second set configured to sense a second value of the image parameter, the method including sampling signals of k pixels of at least one set in a first row to output subsampled signals, converting the subsampled signals into digital signals having a lower resolution than the full frame readout, repeating sampling and converting for k rows, and adding digital signals for the first to kth rows within the at least one set.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 17, 2009
    Inventors: Yong Lim, Kyoung Min Koh, Soo Youn Kim
  • Method of fabricating a dual polysilicon gate of a semiconductor device with a multi-plane channel
    Patent number: 7629219
    Abstract: A dual polysilicon gate of a semiconductor device includes a substrate having a first region, a second region, and a third region, a channel region with a recessed structure formed in the first region of the substrate, a gate insulating layer formed over the substrate, a first polysilicon layer filled into the channel region, and formed over the gate insulating layer of the first and second regions, a second polysilicon layer formed over the gate insulating layer of the third region, and an insulating layer doped with an impurity, and disposed inside the first polysilicon layer in the channel region.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: December 8, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwan-Yong Lim, Heung-Jae Cho, Min-Gyu Sung
  • Method for retransmitting packet in mobile communication system and computer-readable medium recorded program thereof
    Patent number: 7631239
    Abstract: The present invention relates to a method for retransmitting a packet in a mobile communication system. A waiting time for retransmission is established when a packet transmitted from a transmission unit to a receipt unit has no ACK message. A maximum number of times for retransmitting the packet is established when an NACK message is received. The ARQ transmitter moves to a discard state when the maximum management time of the ARQ block expires or the number of times of retransmissions exceeds the maximum number of times of retransmissions, and checks the ACK message receipt. The packet in the transmission buffer is discarded regardless of whether the distant message is transmitted or the discard message is transmitted or the discard message is checked when the ACK message is received.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: December 8, 2009
    Assignees: Electronics and Telecommunications Research Institute, Samsung Electronics Co., Ltd., KT Corporation, SK Telecom Co., Ltd., KT FREETEL Co., Ltd., Hanaro Telecom., Inc.
    Inventors: Kun-Min Yeo, Chul-Sik Yoon, Jae-Heung Kim, Soon-Yong Lim, Byung-Han Ryu
  • Plasma display panel
    Patent number: 7626334
    Abstract: A plasma display panel includes a first substrate and a second substrate that partially define a plurality of discharge cells in a space therebetween, and an electrode structure including an address electrode extending along a first direction, a dielectric layer formed on the address electrode, a first electrode extending along a second direction intersecting the first direction, and a second electrode extending along the second direction intersecting the first direction, where the first electrode and the second electrode are electrically insulated from the address electrode, and at least a portion of each of the first electrode and the second electrode is associated with each of the discharge cells. At least one of the address electrode and the dielectric layer associated with each of the discharge cells may include a first portion and a second portion.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: December 1, 2009
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Min Hur, Jae-Yong Lim
  • Spacer-less low-k dielectric processes
    Patent number: 7615427
    Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: November 10, 2009
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
  • Double anneal with improved reliability for dual contact etch stop liner scheme
    Patent number: 7615433
    Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 10, 2009
    Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines (IBM)
    Inventors: Khee Yong Lim, Victor Chan, Eng Hua Lim, Wenhe Lin, Jamin F. Fen
  • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH INTERFACE BARRIER
    Publication number: 20090239376
    Abstract: A method for fabricating a semiconductor memory device includes forming a first layer, injecting a tungsten source gas and a silicon source gas simultaneously to form a tungsten silicide layer over the first layer, forming a tungsten nitride layer over the tungsten silicide layer without a post purge process of additionally supplying the silicon source gas, and forming a second layer over the tungsten nitride layer.
    Type: Application
    Filed: June 30, 2008
    Publication date: September 24, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Yong-Soo Kim, Kwan-Yong Lim