Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
A semiconductor device is made by forming contact pads on a sacrificial carrier. The contact pads may be formed on a pillar. A semiconductor die is mounted to electrically connect to the contact pads with solder bumps or wire bonds. The semiconductor die is encapsulated with molding compound. The sacrificial carrier is removed. A backside interconnect structure has a first conductive layer formed over the molding compound to electrically connect to the contact pads. A first insulating layer is formed over the first conductive layer. A portion of the first insulating layer is removed to expose the first conductive layer. Solder material is deposited in electrical contact with the first conductive layer. The solder material is reflowed to form a solder bump. A wire bond electrically connects to a contact pad. A front-side interconnect structure can be formed through the molding compound to the contact pads.
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The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming the device using a sacrificial carrier.
BACKGROUND OF THE INVENTIONSemiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level chip scale packages (WLCSP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
In many applications, it is desirable to stack WLCSPs. Appropriate electrical interconnect must be provided for complete device integration. The interconnect typically involves formation of redistribution layers (RDL) and other conductive lines and tracks. These metal lines have limited pitch and line spacing due to etching processing. The formation of the interconnect structure requires a high degree of alignment accuracy in attaching the die to the wafer carrier for subsequent encapsulation and further RDL buildup processes.
A need exists to form the interconnect structures for WLCSPs while accounting for the interconnect alignment requirements.
SUMMARY OF THE INVENTIONIn one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a sacrificial carrier, forming a plurality of contact pads on the sacrificial carrier, mounting a first semiconductor die to electrically connect to the contact pads, encapsulating the first semiconductor die with molding compound, removing the sacrificial carrier, forming a first conductive layer over the molding compound in electrical contact with the contact pads, forming a first insulating layer over the first conductive layer, removing a portion of the first insulating layer to expose the first conductive layer, depositing solder material in electrical contact with the first conductive layer, and reflowing the solder material to form a solder bump.
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a sacrificial carrier, forming a plurality of contact pads on the sacrificial carrier, mounting a first semiconductor die to electrically connect to the contact pads, encapsulating the first semiconductor die with molding compound, forming a first conductive layer over the molding compound in electrical contact with the contact pads, forming a first insulating layer over the first conductive layer, and removing a portion of the first insulating layer to expose the first conductive layer.
In another embodiment, the present invention is a method of making a semiconductor package comprising the steps of providing a sacrificial carrier, forming a plurality of contact pads on the sacrificial carrier, mounting a first semiconductor die to electrically connect to the contact pads, encapsulating the first semiconductor die with molding compound, and forming an interconnect structure over the molding compound in electrical contact with the contact pads.
The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing one or more electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.
A semiconductor wafer generally includes an active surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon. The active side surface contains a plurality of semiconductor die. The active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment. In the layering process, semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Photolithography involves the masking of areas of the surface and etching away undesired material to form specific structures. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation.
Flip chip semiconductor packages and wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count. Flip chip style semiconductor device 10 involves mounting an active area 12 of die 14 facedown toward a chip carrier substrate or printed circuit board (PCB) 16, as shown in
Further detail of forming a semiconductor package in accordance with semiconductor device 10 is shown in
In
In
In
In
Process carrier 50 and adhesive layer 48 are removed. Alternatively, process carrier 50 and adhesive layer 48 can remain attached to the semiconductor device and operate as a heat sink for thermal dissipation or electromagnetic interference (EMI) barrier.
Another embodiment of the initial stages of making the semiconductor device is shown in
In
The interconnect structure is then formed using the steps described in
A process carrier is applied to a backside of the semiconductor die using an adhesive layer to support the package. A conductive layer 102 is selectively plated on a surface of molded compound 101 using an adhesion layer, such as Ti. Conductive layer 102 electrically connects to contact pads 94 according to the electrical function and interconnect requirements of semiconductor die 90 and 98.
An insulating layer 103 is formed over molding compound 101 and conductive layer 102. The insulating layer 103 can be made with material having dielectric properties. A portion of insulating layer 103 is removed by an etching process to form openings and expose conductive layer 102. A conductive layer 104 is formed over insulating layer 103 to electrically contact conductive layer 102. An insulating layer 106 is formed over conductive layer 104 and insulating layer 103. The insulating layer 106 can be made with material having dielectric properties. A portion of insulating layer 106 is removed by an etching process to form openings and expose conductive layer 104. Conductive layers 104 and 106 and insulating layers 103 and 106 constitute a portion of an interconnect structure to route electrical signals between semiconductor die 90 and 98 as well as external to the package. Additional insulating layers and conductive layers can be used in the interconnect structure.
An electrically conductive solder material is deposited over conductive layer 104 through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof. The solder material is reflowed by heating the conductive material above its melting point to form spherical balls or bumps 108. In some applications, solder bumps 108 are reflowed a second time to improve electrical contact to conductive layer 104. An additional under bump metallization can optionally be formed under solder bumps 108. The interconnections can be solder bumps or bond wires.
A process carrier is applied to a backside of the semiconductor die using an adhesive layer to support the package. A conductive layer 136 is selectively plated on a surface of molded compound 130 using an adhesion layer, such as Ti. Conductive layer 136 electrically connects to contact pads 124 according to the electrical function and interconnect requirements of semiconductor die 120 and 126.
An insulating layer 138 is formed over molding compound 130 and conductive layer 136. The insulating layer 138 can be made with materials having dielectric properties. A portion of insulating layer 138 is removed by an etching process to form openings and expose conductive layer 136. A conductive layer 140 is formed over insulating layer 138 to electrically contact conductive layer 136. An insulating layer 142 is formed over conductive layer 140 and insulating layer 138. The insulating layer 142 can be made with material having dielectric properties. A portion of insulating layer 142 is removed by an etching process to form openings and expose conductive layer 140. Conductive layers 136 and 140 and insulating layers 138 and 142 constitute a portion of a front-side interconnect structure which routes electrical signals between semiconductor die 120 and 126, as well as external to the package. Additional insulating layers and conductive layers can be used in the front-side interconnect structure.
A front-side process carrier 146 is mounted to conductive layer 140 and insulating layer 142 using adhesive layer 144. The adhesive layer 144 can be made with thermally or UV light releasable temporary adhesive, typically having a Tg of at least 150° C. The front-side process carrier can be flexible tape or stiff material. The backside process carrier is removed. Vias are formed through molding compound 130 using laser drilling or deep reactive ion etch (DRIE). The vias expose contact pads 124. Conductive material 148 is deposited in the vias and electrically connects to contact pads 124. An insulating layer 150 is formed over conductive layer 148 and molding compound 130. The insulating layer 150 can be made with material having dielectric properties. A portion of insulating layer 150 is removed by an etching process to form openings and expose conductive layer 148. Conductive layer 148 and insulating layer 150 constitute a portion of a backside interconnect structure which routes electrical signals between semiconductor die 120 and 126, as well as external to the package. Additional insulating layers and conductive layers can be used in the backside interconnect structure.
In
The semiconductor device in
In
In
In summary, the semiconductor device employs a copper sheet as a dummy or sacrificial carrier. A plurality of wettable contact pads is patterned on the sacrificial carrier. The individual semiconductor die are mounted to the sacrificial carrier and are electrically connected to the contact pads. The semiconductor die and contact pads are encapsulated with a molding compound. The sacrificial carrier is removed to expose the metal pads. An interconnect build-up layer is formed on the contact pads. The wettable contact pads are selectively plated on the sacrificial metal carrier to provide a highly accurate alignment of the bonding pad positions for the electrical interconnect according to the electrical function of the semiconductor die. By forming contact pads on the sacrificial carrier, a precise placement and alignment for the later formed requisite interconnect structure can be achieved. Accordingly, the semiconductor package has greater interconnect density and lower line pitch for individual traces.
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
Claims
1. A method of making a semiconductor device, comprising:
- providing a first sacrificial metal carrier;
- forming a photoresist layer over the first sacrificial metal carrier;
- forming openings in the photoresist layer extending to the first sacrificial metal carrier;
- forming conductive pillars in the openings of the photoresist layer;
- forming a plurality of contact pads over the conductive pillars, the contact pads being selectively electroplated through the openings in the photoresist layer onto the conductive pillars to provide precise alignment of the contact pads for electrical interconnect, the conductive pillars and first sacrificial metal carrier providing a plating current path for electroplating the contact pads;
- removing the photoresist layer;
- mounting a first semiconductor die to electrically connect to the contact pads;
- encapsulating the first semiconductor die, contact pads, and conductive pillars with molding compound;
- removing the first sacrificial metal carrier;
- mounting a second sacrificial carrier over a first side of the molding compound opposite the contact pads;
- forming a first conductive layer over a second side of the molding compound opposite the first side of the molding compound, the first conductive layer being electrically connected to the contact pads;
- forming a first insulating layer over the first conductive layer and molding compound;
- removing a portion of the first insulating layer to expose the first conductive layer;
- forming a second conductive layer over the first conductive layer and first insulating layer;
- forming a second insulating layer over the first insulating layer and second conductive layer;
- removing a portion of the second insulating layer to expose the second conductive layer; depositing solder material in electrical contact with the second conductive layer;
- reflowing the solder material to form a solder bump;
- removing the second sacrificial carrier;
- forming vias through the first side of the molding compound to the contact pads, the vias having a reduced depth due to the conductive pillars;
- forming a third conductive layer over the molding compound and sidewalls of the vias to electrically connect to the contact pads;
- forming a third insulating layer over the molding compound and third conductive layer, the third insulating layer extending into the vias to cover the third conductive layer; and
- removing a portion of the third insulating layer to expose the third conductive layer.
2. The method of claim 1, further including forming a wire bond electrically connected to one of the plurality of contact pads.
3. The method of claim 1, wherein the first semiconductor die electrically connects to the contact pads with solder bumps or wire bonds.
4-5. (canceled)
6. The method of claim 1, further including:
- mounting a second semiconductor die to the solder bump; and
- encapsulating the second semiconductor die with molding compound.
7. (canceled)
8. A method of making a semiconductor device, comprising:
- providing a sacrificial metal carrier;
- forming a photoresist layer over the sacrificial metal carrier;
- forming openings in the photoresist layer extending to the sacrificial metal carrier;
- forming a plurality of contact pads on the sacrificial carrier, the contact pads being selectively electroplated through the openings in the photoresist layer onto the sacrificial metal carrier to provide precise alignment of the contact pads for electrical interconnect, the sacrificial metal carrier providing a plating current path for electroplating the contact pads;
- removing the photoresist layer;
- mounting a first semiconductor die to electrically connect to the contact pads;
- encapsulating the first semiconductor die with molding compound;
- removing the sacrificial metal carrier;
- mounting a second sacrificial carrier over a first side of the molding compound opposite the contact pads;
- forming a first conductive layer over a second side of the molding compound opposite the first side of the molding compound, the first conductive layer being electrically connected to the contact pads;
- forming a first insulating layer over the first conductive layer;
- removing the second sacrificial carrier;
- forming vias through the first side of the molding compound to the contact pads;
- forming a second conductive layer over the molding compound and into the vias to electrically connect to the contact pads; and
- forming a second insulating layer over the molding compound and second conductive layer
9. The method of claim 8, further including:
- depositing solder material on the first conductive layer; and
- reflowing the solder material to form a solder bump.
10. The method of claim 9, further including:
- mounting a second semiconductor die to the solder bump; and
- encapsulating the second semiconductor die with molding compound.
11. (canceled)
12. The method of claim 8, wherein the first semiconductor die electrically connects to the contact pads with solder bumps or wire bonds.
13-15. (canceled)
16. A method of making a semiconductor package, comprising:
- providing a sacrificial metal carrier;
- forming a photoresist layer over the sacrificial metal carrier;
- forming openings in the photoresist layer extending to the sacrificial metal carrier;
- forming a plurality of contact pads on the sacrificial carrier, the contact pads being selectively electroplated through the openings in the photoresist layer onto the sacrificial metal carrier to provide precise alignment of the contact pads for electrical interconnect, the sacrificial metal carrier providing a plating current path for electroplating the contact pads;
- mounting a first semiconductor die to electrically connect to the contact pads;
- encapsulating the first semiconductor die with molding compound; and
- forming an interconnect structure over the molding compound and electrically connected to the contact pads.
17. The method of claim 16, wherein forming the interconnect structure includes:
- forming a first conductive layer over the molding compound and electrically connected to the contact pads;
- forming a first insulating layer over the first conductive layer; and
- removing a portion of the first insulating layer to expose the first conductive layer.
18. The method of claim 17, further including:
- forming a second conductive layer over the first insulating layer and electrically connected to the first conductive layer;
- forming a second insulating layer over the second conductive layer; and
- removing a portion of the second insulating layer to expose the second conductive layer.
19. The method of claim 18, further including mounting a front-side process carrier to the second insulating layer with an adhesive layer.
20. The method of claim 19, further including:
- forming vias through the molding compound to the contact pads;
- forming a second conductive layer in the vias to electrically connect to the contact pads;
- forming a second insulating layer over the second conductive layer; and
- removing a portion of the second insulating layer to expose the second conductive layer.
21. The method of claim 17, further including:
- depositing solder material on the first conductive layer; and
- reflowing the solder material to form a solder bump.
22. The method of claim 16, further including removing the sacrificial carrier.
23. The method of claim 16, wherein the first semiconductor die electrically connects to the contact pads with solder bumps or wire bonds.
24. The method of claim 16, further including forming a pillar under each of the plurality of contact pads.
Type: Application
Filed: Dec 26, 2007
Publication Date: Jul 2, 2009
Applicant: STATS CHIPPAC, LTD. (Singapore)
Inventors: Il Kwon Shim (Singapore), Yaojian Lin (Singapore), Seng Guan Chow (Singapore)
Application Number: 11/964,397
International Classification: H01L 21/56 (20060101);