Deposition Of Layer Comprising Metal, E.g., Metal, Alloys, Metal Compounds (epo) Patents (Class 257/E21.295)
  • Patent number: 10903276
    Abstract: The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tsz Wah Chan, Yongjun J. Hu, Swapnil Lengade
  • Patent number: 10892224
    Abstract: Some embodiments include an apparatus having a structure with a surface which comprises tungsten. The apparatus has titanium-nitride-containing protective material along and directly against the surface. The structure may be a digit line of a memory array. Some embodiments include a method in which an assembly is formed to have a tungsten-containing layer with an exposed tungsten-containing upper surface. Titanium-nitride-containing protective material is formed over and directly against the tungsten-containing upper surface. Additional material is formed over the protective material, and is spaced from the tungsten-containing upper surface by the protective material. The additional material may comprise silicon nitride and/or silicon dioxide.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Luca Fumagalli, Davide Colombo
  • Patent number: 10510805
    Abstract: The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tsz Wah Chan, Yongjun J. Hu, Swapnil Lengade
  • Patent number: 10319582
    Abstract: Thin layer of silicon oxide is deposited on a substrate having an exposed layer of metal (e.g., W, Cu, Ti, Co, Ta) without causing substantial oxidation of the metal. The method involves: (a) contacting the substrate having an exposed metal layer with a silicon-containing precursor and adsorbing the precursor on the substrate; (b) removing the unadsorbed precursor from a process chamber; and (c) contacting the adsorbed precursor with a plasma formed in a process gas comprising an oxygen source (e.g., O2, CO2, N2O, O3) and H2, to form silicon oxide from the silicon-containing precursor while suppressing metal oxidation. These steps can be repeated until a silicon oxide film of a desired thickness is formed. In some embodiments, the silicon oxide film is used to improve nucleation of subsequently deposited silicon carbide.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 11, 2019
    Assignee: Lam Research Corporation
    Inventors: Bhadri N. Varadarajan, Zhe Gui, Bo Gong, Andrew John McKerrow
  • Patent number: 10115634
    Abstract: A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9859219
    Abstract: An interconnect structure including at least one copper wiring is formed embedded in an interconnect dielectric material layer. A copper titanium alloy is in direct physical contact with sidewalls, a bottommost surface and a topmost surface of the copper structure.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 9754822
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Patent number: 9607853
    Abstract: A patterning method using a metal mask includes sequentially forming a lower metal layer and an upper metal layer on an etching object layer, forming an upper metal mask, forming the upper metal mask including patterning the upper metal layer, forming a lower metal mask, forming the lower metal mask including patterning the lower metal layer using the upper metal mask, and patterning the etching object layer using the upper metal mask.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-yub Jeon, Dong-chan Kim, Gyung-jin Min, Jae-hong Park, Je-woo Han
  • Patent number: 9593019
    Abstract: Certain example embodiments relate to methods for large area graphene precipitation onto glass, and associated articles/devices. For example, coated articles including graphene-inclusive films on substrates, and/or methods of making the same, are provided. A metal-inclusive catalyst layer (e.g., of or including Ni and/or the like) is disposed on the substrate. The substrate with the catalyst layer thereon is exposed to a precursor gas and a strain-inducing gas at a temperature of no more than 350-600 degrees C. for 10s or 100s of minutes. Graphene is formed and/or allowed to form both over and contacting the catalyst layer, and between the substrate and the catalyst layer, in making the coated article. The catalyst layer, together with graphene formed thereon, is removed, e.g., through excessive strain introduced into the catalyst layer as associated with the graphene formation. Products including such articles, and/or methods of making the same, also are contemplated.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: March 14, 2017
    Assignee: Guardian Industries Corp.
    Inventor: Vijayen S. Veerasamy
  • Patent number: 9034749
    Abstract: A gate structure is provided on a channel portion of a semiconductor substrate. The gate structure may include an electrically conducting layer present on a gate dielectric layer, a semiconductor-containing layer present on the electrically conducting layer, a metal semiconductor alloy layer present on the semiconductor-containing layer, and a dielectric capping layer overlaying the metal semiconductor alloy layer. In some embodiments, carbon and/or nitrogen can be present within the semiconductor-containing layer, the metal semiconductor alloy layer or both the semiconductor-containing layer and the metal semiconductor alloy layer. The presence of carbon and/or nitrogen within the semiconductor-containing layer and/or the metal semiconductor alloy layer provides stability to the gate structure. In another embodiment, a layer of carbon and/or nitrogen can be formed between the semiconductor-containing layer and the metal semiconductor alloy layer.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas L. Breil, Cyril Cabral, Jr., Martin M. Frank, Claude Ortolland
  • Patent number: 9018086
    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin, Min-Chuan Tsai, Wei-Yu Chen, Chien-Hao Chen
  • Patent number: 9000416
    Abstract: A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. The nanoparticle can be formed with a barrier separating it from another nanoparticle on the substrate; for example, nanoparticle can be located in a pit etched in the substrate. The size and location of the nanoparticle can be stable at elevated temperatures.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: April 7, 2015
    Assignee: Massachusetts Institute of Technology
    Inventors: Silvija Gradecak, Chun-Hao Tseng, Sung Keun Lim
  • Patent number: 8987148
    Abstract: With a stage kept in an as-heated state, a semiconductor wafer is placed over the stage. Then, with the elapse of a first time, a controller causes a pressure inside a vacuum chamber to rise to a second pressure higher than a first pressure (step S40). After the semiconductor wafer is placed over the stage, a pressure difference between a pressure inside the vacuum chamber and a pressure inside an adsorption port is set to a minimum value at which the semiconductor wafer is not allowed to slide over protrusions. Further, in step S40 as well, the pressure difference is kept at the minimum value at which the semiconductor wafer is not allowed to slide over the protrusions.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Misato Sakamoto, Yoshitake Katou, Youichi Yamamoto, Takashi Kyouno, Chikara Yamamoto, Terukazu Motosawa, Mitsuo Maeda, Hiroshi Itou
  • Patent number: 8921222
    Abstract: A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 8900999
    Abstract: A method of filling a feature in a substrate with tungsten without forming a seam is presented. The tungsten is deposited by a thermal chemical vapor deposition (CVD) process using hydrogen (H2) and tungsten hexafluoride (WF6) precursor gases. The H2 to WF6 flow rate ratio is greater than 40 to 1, such as from 40 to 1 to 100 to 1. The substrate temperature during deposition is less than 300 degrees Celsius (° C.) and the processing pressure during deposition is greater than 300 Torr.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 2, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kai Wu, Sang-Hyeob Lee, Joshua Collins, Kiejin Park
  • Patent number: 8883641
    Abstract: The present invention relates to a solution and a method for activating the oxidized surface of a substrate, in particular of a semiconducting substrate, for its subsequent coating by a metal layer deposited by the electroless method. According to the invention, this composition contains: A) an activator consisting of one or more palladium complexes; B) a bifunctional organic binder consisting one or more organosilane complexes; C) a solvent system consisting one or more solvents for solubilizing the said activator and the said binder.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 11, 2014
    Assignee: Alchimer
    Inventors: Vincent Mevellec, Dominique Suhr
  • Patent number: 8853075
    Abstract: Methods of forming titanium-containing layers on substrates are disclosed. In the disclosed methods, the vapor of a precursor compound having the formula Ti(Me5Cp)(OR)3, wherein R is selected from methyl, ethyl, or isopropyl is provided. The vapor is reacted with the substrate according to an atomic layer deposition process to form a titanium-containing complex on the surface of the substrate.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 7, 2014
    Assignee: L'Air Liquide Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Satoko Gatineau, Christian Dussarrat, Christophe Lachaud, Nicolas Blasco, Audrey Pinchart, Ziyun Wang, Jean-Marc Girard, Andreas Zauner
  • Patent number: 8835233
    Abstract: A method for fabricating a multiple-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches. Still further, the method includes depositing a third workfunction material in a layer in the plurality of trenches.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 16, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Andy C. Wei, Akshey Sehgal, Bamidele S. Allimi
  • Patent number: 8803319
    Abstract: A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 8765610
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of second core films, the second core film having a first array portion, and a second array portion which is arranged so as to be spaced at a larger second space than the first space in the first direction from the first array portion, the second space being positioned above the loop portion. The method includes processing the second film to be processed below the first array portion into a second line and space pattern which includes a second line pattern extending in the second direction, and removing the second film to be processed below the second space and the loop portion of the first film to be processed, by an etching using the second spacer film as a mask.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masato Shini
  • Patent number: 8759949
    Abstract: An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hon-Lin Huang, Kuo-Ching Hsu, Chen-Shien Chen
  • Patent number: 8728935
    Abstract: A method of manufacturing a semiconductor device capable of minimally preventing the property deterioration caused by the oxidation of a metal film, and a substrate processing apparatus are provided.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: May 20, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiro Harada, Hideharu Itatani, Sadayoshi Horii
  • Patent number: 8716132
    Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, exposing the patterned substrate to a process gas comprising a metal-containing precursor, and irradiating the patterned substrate with electromagnetic radiation, where selective metal-containing cap layer formation on the Cu metal surfaces is facilitated by the electromagnetic radiation. In some embodiments, the method further includes pre-treating the patterned substrate with additional electromagnetic radiation and optionally a cleaning gas prior to forming the metal-containing cap layer.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: May 6, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Shigeru Mizuno
  • Publication number: 20140117509
    Abstract: Various techniques, methods and devices are disclosed where metal is deposited on a substrate, and stress caused by the metal to the substrate is limited, for example to limit a bending of the wafer.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Manfred Schneegans, Juergen Foerster, Bernhard Weidgans, Norbert Urbansky, Tilo Rotth
  • Publication number: 20140099784
    Abstract: A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn KIM, JE-DON KIM
  • Patent number: 8685849
    Abstract: A semiconductor device in one embodiment includes a depletion junction, a peripheral region adjacent the depletion junction, and a buffer layer. The buffer layer is adapted to reduce localization of avalanche breakdown proximate the interface between the depletion junction and the peripheral region.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 1, 2014
    Assignee: Siliconix Technology C. V. IR
    Inventors: Andrea Irace, Giovanni Breglio, Paolo Spirito, Andrea Bricconi, Diego Raffo, Luigi Merlin
  • Patent number: 8685866
    Abstract: A method of manufacturing a semiconductor device including alternately repeating a process of forming a first metal oxide film including a first metal element and a process of forming a second metal oxide film including a second metal element on a substrate accommodated in a processing chamber, so as to form a third metal oxide film including the first and second metal elements with a predetermined composition ratio on the substrate. One of the first and second metal elements of the third metal oxide film has a concentration higher than a concentration of the other, and one of the first and second metal oxide films including the higher-concentration metal element is formed in a chemical vapor deposition (CVD) mode or an atomic layer deposition (ALD) saturation mode, and the other of the first and second metal oxide films is formed in an ALD unsaturation mode.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 1, 2014
    Assignees: Hitachi Kokusai Electric, Inc., Renesas Electronics Corp.
    Inventors: Sadayoshi Horii, Atsushi Sano, Masahito Kitamura, Yoshitake Kato
  • Publication number: 20140084948
    Abstract: Provided are test vehicles for evaluating various semiconductor materials. These materials may be used for various integrated circuit components, such as embedded resistors of resistive random access memory cells. Also provided are methods of fabricating and operating these test vehicles. A test vehicle may include two stacks protruding through an insulating body. Bottom ends of these stacks may include n-doped poly-silicon and may be interconnected by a connector. Each stack may include a titanium nitride layer provided over the poly-silicon end, followed by a titanium layer over the titanium nitride layer and a noble metal layer over the titanium layer. The noble metal layer extends to the top surface of the insulating body and forms a contact surface. The titanium layer may be formed in-situ with the noble metal layer to minimize oxidation of the titanium layer, which is used as an adhesion and oxygen getter.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Mihir Tendulkar, David Chi
  • Publication number: 20140080304
    Abstract: An integrated tool to reduce defects in manufacturing a semiconductor device by reducing queue times during a manufacturing process. The integrated tool may include at least one a polishing tool comprising at least one polishing module and at least one deposition tool comprising at least one deposition chamber. At least one pump-down chamber may connect the polishing tool to the deposition tool. The at least one pump-down chamber includes a passage through which the semiconductor device is passed. Defects in the semiconductor device are reduced by reducing the queue time at various stages of the fabrication process.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 8647918
    Abstract: Methods of forming a graphene material on a surface are presented. A metal material is disposed on a material substrate or material layer and is infused with carbon, for example, by exposing the metal to a carbon-containing vapor. The carbon-containing metal material is annealed to cause graphene to precipitate onto the bottom of the metal material to form a graphene layer between the metal material and the material substrate/material layer and also onto the top and/or sides of the metal material. Graphene material is removed from the top and sides of the metal material and then the metal material is removed, leaving only the graphene layer that was formed on the bottom of the metal material. In some cases graphene material that formed on one or more side of the sides of the metal material is not removed so that a vertical graphene material layer is formed.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 11, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis Anderson, Boris N. Feygelson
  • Patent number: 8637925
    Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Asa Frye, Andrew Simon
  • Patent number: 8637396
    Abstract: A method is provided for depositing a dielectric barrier film including a precursor with silicon, carbon, oxygen, and hydrogen with improved barrier dielectric properties including lower dielectric constant and superior electrical properties. This method will be important for barrier layers used in a damascene or dual damascene integration for interconnect structures or in other dielectric barrier applications. In this example, specific structural properties are noted that improve the barrier performance.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: January 28, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Laura M. Matz, Raymond Nicholas Vrtis, Mark Leonard O'Neill, Dino Sinatore
  • Patent number: 8623764
    Abstract: Compositions and methods for forming metal films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing at least one metal precursor comprising at least one ligand, an excess amount of neutral labile ligands, a supercritical solvent, and optionally at least one source of B, C, N, Si, P, and mixtures thereof; exposing the composition to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; disassociating the at least one ligand from the metal precursor; and forming the metal film while minimizing formation of metal oxides.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: January 7, 2014
    Assignee: Lam Research Corporation
    Inventor: Mark Ian Wagner
  • Patent number: 8623733
    Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: January 7, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Raashina Humayun, Michal Danek, Anand Chandrashekar
  • Patent number: 8592312
    Abstract: In one disclosed embodiment, the present method for depositing a conductive capping layer on metal lines comprises forming metal lines on a dielectric layer, applying a voltage to the metal lines, and depositing the conductive capping layer on the metal lines. The applied voltage increases the selectivity of the deposition process used, thereby preventing the conductive capping layer from causing a short between the metal lines. The conductive capping layer may be deposited through electroplating, electrolessly, by atomic layer deposition (ALD), or by chemical vapor deposition (CVD), for example. In one embodiment, the present method is utilized to fabricate a semiconductor wafer. In one embodiment, the metal lines comprise copper lines, while the conductive capping layer may comprise tantalum or cobalt. The present method enables deposition of a capping layer having high electromigration resistance.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: November 26, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: E. Todd Ryan, John A. Iacoponi
  • Patent number: 8580672
    Abstract: One illustrative method disclosed herein includes forming a conductive pad in a layer of insulating material, forming a passivation layer above the conductive pad, performing at least one etching process on the passivation layer to define an opening in the passivation layer that exposes at least a portion of the conductive pad, forming a protective layer on the passivation layer, in the opening and on the exposed portion of the conductive pad, forming a heat-curable material layer above the protective layer, performing an etching process to define a patterned heat-curable material layer having an opening that exposes a portion of the protective layer, performing an etching process on the protective layer to thereby expose at least a portion of the conductive pad and forming a conductive bump that is conductively coupled to the conductive pad.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: November 12, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Kuechenmeister, Lothar Lehmann, Alexander Platz, Gotthard Jungnickel, Sven Kosgalwies
  • Patent number: 8580671
    Abstract: A method of manufacturing a semiconductor device of the present invention includes a first step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminum, zirconium, strontium, titanium, barium, tantalum, niobium, on a substrate having a metal thin film formed on the surface, at a first temperature allowing no oxidization of the metal thin film to occur, and allowing the metal oxide film to be set in an amorphous state; and a second step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminum, zirconium, strontium, titanium, barium, tantalum, niobium on the metal oxide film formed in the first step, up to a target film thickness, at a second temperature exceeding the first temperature.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: November 12, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Sadayoshi Horii, Yoshinori Imai, Mika Karasawa
  • Publication number: 20130277826
    Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.
    Type: Application
    Filed: December 3, 2010
    Publication date: October 24, 2013
    Applicant: STATS CHIPPAC, LTD.
    Inventor: Rajendra D. Pendse
  • Patent number: 8546945
    Abstract: A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 8541276
    Abstract: A dielectric containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric produce a reliable dielectric for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium aluminum oxide film.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8541307
    Abstract: A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH3 gas under a plasma condition so as to reduce copper oxide (CuO) to copper (Cu) formed on the deposition layer of copper; in the reaction chamber, generating an etching block layer on the deposition layer of copper using a DDSN deposition process; cleaning the reaction chamber using NF3 gas; and directing N2O gas into the reaction chamber and removing the remaining hydrogen (H) and fluorine (F) in the reaction chamber using the N2O gas under the plasma condition.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 24, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Meimei Gu, Duoyuan Hou, Jun Xu, Ke Wang
  • Publication number: 20130200496
    Abstract: The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some embodiments the method comprises implanting the top surface of a donor body with an ion dosage to form a cleave plane followed by exfoliating a lamina from the donor body. After exfoliating the lamina, a flexible metal support that has a coefficient of thermal expansion with a value that is within 10% of the value of the coefficient of thermal expansion of the lamina is constructed on the lamina. In some embodiments the coefficients of thermal expansion of the metal support and the lamina are within 10% or within 5% of each other between the temperatures of 100 and 600 ° C.
    Type: Application
    Filed: July 26, 2012
    Publication date: August 8, 2013
    Applicant: TWIN CREEKS TECHNOLOGIES, INC.
    Inventors: Venkatesan Murali, Thomas Edward Dinan, JR., Steve Bababyan, Gopal Prabhu
  • Patent number: 8501531
    Abstract: Methods of forming a graphene material on a surface are presented. A metal material is disposed on a material substrate or material layer and is infused with carbon, for example, by exposing the metal to a carbon-containing vapor. The carbon-containing metal material is annealed to cause graphene to precipitate onto the bottom of the metal material to form a graphene layer between the metal material and the material substrate/material layer and also onto the top and/or sides of the metal material. Graphene material is removed from the top and sides of the metal material and then the metal material is removed, leaving only the graphene layer that was formed on the bottom of the metal material. In some cases graphene material that formed on one or more side of the sides of the metal material is not removed so that a vertical graphene material layer is formed.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: August 6, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis Anderson, Boris N. Feygelson
  • Patent number: 8497142
    Abstract: Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: July 30, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Jun-Kyu Yang, Young-Geun Park, Ki-Hyun Hwang, Han-Mei Choi, Dong-Chul Yoo
  • Publication number: 20130095649
    Abstract: Ions depleted from a chemical bath by a reaction such as plating are continually replenished by production and moving of ions through selectively permeable membranes while isolating potential contaminant ions from the chemical bath.
    Type: Application
    Filed: October 17, 2011
    Publication date: April 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tien-Jen Cheng, John Anthony Fitzsimmons, David E. Speed, Keith Kwong Hon Wong
  • Publication number: 20130084701
    Abstract: A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH3 gas under a plasma condition so as to reduce copper oxide(CuO) to copper(Cu) formed on the deposition layer of copper; in the reaction chamber, generating an etching block layer on the deposition layer of copper using a DDSN deposition process; cleaning the reaction chamber using NF3 gas; and directing N2O gas into the reaction chamber and removing the remaining hydrogen (H) and fluorine (F) in the reaction chamber using the N2O gas under the plasma condition.
    Type: Application
    Filed: December 29, 2011
    Publication date: April 4, 2013
    Applicant: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Meimei GU, Duoyuan HOU, Jun XU, Ke WANG
  • Patent number: 8399313
    Abstract: A gate electrode is formed by forming a first conductive layer containing aluminum as its main component over a substrate, forming a second conductive layer made from a material different from that used for forming the first conductive layer over the first conductive layer; and patterning the first conductive layer and the second conductive layer. Further, the first conductive layer includes one or more selected from carbon, chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel. And the second conductive layer includes one or more selected from chromium, tantalum, tungsten, molybdenum, titanium, silicon, and nickel, or nitride of these materials.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: March 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Hotaka Maruyama
  • Patent number: 8389393
    Abstract: A noble metal nanoparticle can be grown on a semiconductor substrate by contacting a predetermined region of the substrate with a solution including noble metal ions. The predetermined region of the semiconductor substrate can be exposed by applying a polymeric layer over the substrate selectively removing a portion of the polymeric layer. The nanoparticles can be prepared in a predetermined pattern. The nanoparticle can be formed with a barrier separating it from another nanoparticle on the substrate; for example, nanoparticle can be located in a pit etched in the substrate. The size and location of the nanoparticle can be stable at elevated temperatures.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: March 5, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Silvija Grade{hacek over (c)}ak, Chun-Hao Tseng, Sung Keun Lim
  • Publication number: 20130052823
    Abstract: A system is provided that includes a power supply connectable to a semiconductor wafer including opposing, major front and back surfaces joined by a circumferential side, with the wafer undergoing processing including electroplating a damascene layer on the wafer. The system also includes an arrangement configured to apply a polymer coating to the side of the wafer before electroplating the damascene layer, with the system being configured to apply the polymer coating in accordance with an electrophoresis technique driven by the power supply. In this regard, the polymer coating is applied to the side but not at least a portion of the front and back surfaces of the wafer, and the polymer coating provides a barrier to formation of the damascene layer on the side of the wafer.
    Type: Application
    Filed: August 31, 2011
    Publication date: February 28, 2013
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Meng Tsung Ko, Yung Tai Hung, Chin Ta Su
  • Publication number: 20130040449
    Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.
    Type: Application
    Filed: October 16, 2012
    Publication date: February 14, 2013
    Applicant: Texas Instruments Incorporated
    Inventor: Texas Instruments Incorporated