Release Strategies for Making Transferable Semiconductor Structures, Devices and Device Components
Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.
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This application is a continuation of U.S. patent application No. 13/071,027, filed Mar. 24, 2011, which is a continuation of U.S. patent application No. 11/858,788, filed Sep. 20, 2007 (now issued as U.S. Pat. No. 7,932,123), which claims the benefit of U. S. Provisional Application Nos. 60/826,354, filed Sep. 20, 2006 and 60/944,653 filed Jun. 18, 2007, all of which are incorporated by reference to the extent they are not inconsistent with the present disclosure.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
This invention was made with government support under Grant DEFG02-91-ER45439 awarded by Department of Energy. The government has certain rights in the invention.BACKGROUND OF THE INVENTION
A variety of platforms are available for printing structures on device substrates and device components supported by device substrates, including nanostructures, microstructures, flexible electronics, and a variety of other patterned structures. For example, a number of patents and patent applications describe different methods and systems for making and printing a wide range of structures, including U.S. patent application Ser. Nos. 11/115,954, now U.S. Pat. No. 7,195,733 (18-04 filed Apr. 27, 2005); 11/145,574, now U.S. Pat. No. 7,622,367 (38-04A filed Jun. 2, 2005); 11/145,542, now U.S. Pat. No. 7,557,367 (38-04B filed Jun. 2, 2005); 11/423,287, now U.S. Pat. No. 7,521,292 (38-04C filed Jun. 9, 2006); 11/423,192, now U.S. Pat. No. 7,943,491 (41-06 filed Jun. 9, 2006); 11/421,654, now U.S. Pat. No. 7,799,699 (43-06 filed Jun. 1, 2006); 60/826,354 (151-06P filed Sep. 20, 2006), each hereby incorporated by reference to the extent not inconsistent herewith. A need currently exists for methods and structures for generating transferable semiconductor elements. There is a particular need for low cost methods and structures compatible with high-throughput processing to make device and device components.SUMMARY OF THE INVENTION
Methods and related systems are provided to facilitate low-cost generation of structures capable of printing on device substrates or device components on device substrates. This is accomplished by providing stacks of multilayer structures configured to provide access to individual layers. Of particular use are individual layers that are functional layers, where the functional layers are subsequently incorporated into device and device components. Individual layers are accessed by release strategies that provide sequential layer-by-layer access or access to two or more layers simultaneously. Those functional layers are capable of being printed onto, or incorporated into, devices or device components, by a wide range of printing methods and systems. These multilayer stack systems provide a capability to generate multiple printable or transferable functional structures contained in multiple layers in a single process, thereby decreasing the cost per printable or transferable structure or layer and decreasing the final cost of the end device or device component.
In an aspect, the invention provides methods for making low-cost and/or high performance photovoltaics by multilayer structures having a plurality of functional layers that can be incorporated into a solar cell of the photovoltaic. This multilayer approach is advantageous for a number of reasons. For example, multiple solar cells may be grown in a single deposition run, thereby avoiding loading and unloading of growth chambers, growth substrate surface preparation, and the deposition of buffer layers currently required by single layer fabrication approaches. This results in a significant decrease in manufacturing cost per solar cell layer, thereby decreasing the cost to the solar cell device component. In addition, the capability of lifting-off fully functional layers from a mother substrate provides the ability to reuse the mother substrate by constructing additional multilayer structures on the same mother substrate. Furthermore, the multilayer configuration is easily heat sunk and can provide transferable structures that may be readily printed to plastics and other substrates having a wide range of form factors.
In an embodiment, a method is provided for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers. In this configuration, at least a portion of the release layers are positioned between the functional layers to provide access to the functional layers. At least a portion of the functional layers are released from the multilayer structure by separating one or more of the release layers or a portion thereof from one or more of the functional layers. This functional layer release generates a structure capable of being printed onto a substrate. A device or device component is made by printing one or more of these transferable structures onto a device substrate or device component supported by a device substrate by any printing means known in the art (e.g., contact printing, liquid printing, dry transfer contact printing, soft lithographic microtransfer printing and soft lithographic nanotransfer printing, solution printing, fluidic self assembly, ink jet printing, thermal transfer printing, and screen printing), such as by contact printing.
Release is used broadly and refers to any means for separating at least a portion of a layer from other layers in the multilayer structure. For example, the step of releasing at least a portion of a functional layer from a multilayer substructure may be by physically separating at least one pair of adjacent layers. The adjacent layers may be a release layer that is adjacent to a functional layer in the multilayer structure. The release layer is constructed to facilitate release of at least a portion of a functional layer in response to a release stimulus. For example, the release stimulus may comprise a chemical or physical stimulus that removes at least a portion of the release layer, thereby facilitating release of an adjacent functional layer. Any stimulus, however, capable of affecting a targeted release layer may be used. Other examples of releasing steps include, but are not limited to, etching one or more release layers, thermally shocking one or more release layers, ablating one or more release layers by exposure of the release layers to electromagnetic radiation from a laser source, and decomposing one or more release layers by contacting the release layers with a chemical agent. In an aspect, functional layers are connected to adjacent layers by anchoring means located at the ends of the layer, and so release is achieved by undercutting at those ends to lift-off the functional layer. Alternatively, anchors are provided as patterns in a sacrificial layer or release layer, thereby providing anchors fixed to an adjacent layer or a substrate. These anchors provide further flexibility in the design of breakable tether points to facilitate controlled lift-off of functional layer portions. Optionally, in any of the methods disclosed herein, layers that remain attached to the lifted-off functional layer are removed. In an aspect, lift-off is accomplished by contacting the multilayer structure with a stamp, such as an elastomeric stamp. Optionally, a stamp is used to facilitate contact printing of the lift-off structure to a surface.
To facilitate transmission of a signal to a release layer, any one or more of the functional layers through which the signal passes, are capable of at least partially transmitting the signal. For example, for a signal that is electromagnetic radiation, the functional layers are at least partially transparent to electromagnetic radiation that is capable of ablating at least a portion of the release layers. Alternatively, if the electromagnetic radiation is transmitted from an opposite side, such as the other side of the substrate that supports the multilayer structure, the substrate is at least partially transparent to the electromagnetic radiation.
Another means for releasing is an interfacial crack located in a release layer. Such a crack facilitates lift off of one or more functional layers by applying a stress to the system, such as to the release layer. The crack may be introduced by any means known in the art including, but not limited to a mechanical, chemical or thermal-generated force.
In an aspect, any of the methods disclosed herein may further include masking at least a portion of the multilayer structure. For example, a mask layer that is in physical contact with one or more functional layers. Such masks are capable of at least partially preventing exposure of one or more functional layers to an etchant, solvent or chemical agent provided as a release signal to release at least a portion of the functional layers from the multilayer structure. Such a mask may be useful in applications where the functional layer is a high-quality layer that is expensive and prone to damage by the release signal, such as an etchant.
In another aspect, a carrier film is provided in contact with one or more of the functional layers to further facilitate the step of releasing at least a portion of said functional layers from the multilayer substructure.
The methods and systems provided herein are useful for generating a wide range of transferable structures having a wide range of geometry. Accordingly, the method is capable of incorporation into a number of device manufacturing processes for a wide range of device and device component manufacture. In an aspect, the transferable structure has a layer-type geometry. In another aspect, recessed features are provided by any method known in the art so that at least one of the functional layers generates transferable structures having one or more preselected microsized or nanosized physical dimensions. For example, generation of recessed features in at least one of the functional layers is optionally carried out using a patterning technique, such as a patterning technique that is photolithography, soft lithography, electron beam direct writing, or photoablation patterning.
A functional layer of the present invention is used broadly, and refers to material that is of use within a device or device component. A functional layer with wide application for a variety of devices and device components is a multilayer having a semiconductor or a sequence (e.g. plurality) of semiconductor layers. Functional layer composition and geometry is selected depending on the end use or function of that functional layer. For example, the sequence of semiconductor layers can be at least one semiconductor layer selected from the group consisting of: a single crystalline semiconductor layer, an organic semiconductor layer, an inorganic semiconductor layer, a III-V semiconductor layer; and a group IV elemental or compound semiconductor. In another aspect, the sequence of semiconductor layers is at least two semiconductor layers having different semiconductor materials. In an aspect, at least one of the functional layers is made from one or more dielectric layers or one or more conductor layers. In an embodiment, a functional layer in the multilayer may be different than other functional layers. In an embodiment, all the functional layers in the multilayer are the same. In an embodiment, a functional layer in the multilayer is a complex recipe of individual layers, such as a plurality of semiconductor layers. In the drawings included as a part of this application, the structures derived from these functional layers are referred to as “functional materials elements or devices” (FMEDs).
Other functional layers useful in certain methods described herein include, but are not limited to, functional layers that are an electronic, optical or electro-optic device or a component of an electronic, optical, electro-optic device, a component thereof that is a part of a P-N junction, a thin film transistor, a single junction solar cell, a multi-junction solar cell, a photodiode, a light emitting diode, a laser, a CMOS device, a MOSFET device, a MESFET device, or a HEMT device.
In an embodiment, any of the multilayer structures are generated on a substrate. In an aspect, at least one release layer is provided between the multilayer structure and the substrate, such as a release layer positioned between a functional layer and a substrate. In another aspect, a release layer is not provided between the multilayer structure and the substrate. In that case, the mother substrate and/or the adjacent functional layer provide the ability to release the functional layer from the substrate. In an aspect the mother substrate is itself a release layer.
The multilayer structure and specifically the individual layers of the multilayer structure, may be deposited or grown on the substrate surface as known in the art. For example, any one or more means for growing or depositing layers on a surface may be selected from various techniques including but not limited to: epitaxial growth, evaporation deposition, vapor-phase epitaxy, molecular-beam epitaxy, metalorganic chemical vapor deposition, chemical vapor deposition, physical vapor deposition, sputtering deposition, sol-gel coating, electron beam evaporation deposition, plasma-enhanced chemical vapor deposition; atomic layer deposition, liquid phase epitaxy, electrochemical deposition, and spin coating. In such a manner, multiple transferable structures are generated from a system and, upon release of the final functional layer (e.g., the layer closest to the substrate surface), the substrate is optionally reused again. Such reuse results in cost savings compared to manufacturing processes where the substrate itself is either damaged, destroyed, or incorporated into the final device or device component.
The multilayer structure optionally includes a functional layer and/or release layer having a preselected sequence of thin films epitaxially grown on a substrate, such as alternating release layers and functional layers. In an embodiment, the functional layers have thicknesses selected from the range of about 5 nm to about 50,000 nanometers. In an embodiment the multilayer structure has about 2 to about 200 functional layers and/or about 2 to about 200 release layers. The release layer, depending on the system configuration, may be as thin as 1 nm. In other embodiments the release layer may be thicker, for example between about 1 μm and 2 μm The actual selection of the composition of the release layer material is made based on a number of parameters, such as whether it is desired to grow high-quality functional layers (e.g., epitaxial growth). Release layer composition constraint may be relaxed if growth is not epitaxial. In addition, the release layer composition should be compatible with the release strategy for releasing functional layers from the multilayer structure. For example, if the release mechanism is by cracking, Young's modulus may be selected to facilitate optimal cracking.
Many different devices are capable of being made using any of the methods disclosed herein. In an aspect, the invention provides a method of making a photovoltaic device or device array, a transistor device or device array, a light emitting diode device or device array, a laser or array of lasers, a sensor or sensor array, an integrated electronic circuit, a microelectromechanical device or a nanoelectromechanical device.
In an embodiment, any of the methods of the present invention are for making transferable semiconductor structures. For example, transferable semiconductor structures are made from at least a portion of a functional layer having one or more semiconductor thin films, and releasing at least a portion of the functional layers from the multilayer structure by separating one or more of the release layers or a portion thereof from one or more of the functional layers. Similarly, methods are provided for making a photovoltaic device or device array by providing at least a portion of a functional layer that is itself a photovoltaic cell, such as a photovoltaic cell having a preselected sequence of semiconductor thin films.
In another embodiment, the invention is a method for making a device or device component, where a sacrificial layer is provided on at least a portion of a substrate surface. Sacrificial layer is used broadly to refer to a material that facilitates removal of a functional layer from a substrate. The sacrificial layer has a receiving surface for receiving a functional layer material. The sacrificial layer is selectively patterned by any means known in the art to reveal the underlying substrate or film or coating on the substrate in a corresponding pattern. The pattern of exposed substrate corresponds to potential anchor regions of a functional layer when the functional layer is subsequently deposited. In particular, the deposited functional layer has two regions: an “anchor region” that corresponds to the patterned regions in the sacrificial layer and an “unanchored region” where there is a sacrificial layer that separates the functional layer from the underlying substrate. The anchors can function as bridge elements to facilitate controlled lift-off of functional layer in a pattern that corresponds to the unanchored region. A portion of the functional layer is released, wherein the pattern of functional layer anchors remain at least partially anchored to the substrate and at least a portion of the functional layer not anchored to the substrate is released, thereby generating a plurality of transferable structures. The transferable structures are optionally printed onto a device substrate or device component supported by a device substrate, thereby making the device or the device component. Any printing means known in the art may be used, such as contact printing or solution printing, as described herein.
In an embodiment, the releasing step comprises contacting an elastomeric stamp to at least a portion of the functional layer and removing the stamp from contact with the functional layer, thereby removing at least a portion of the functional layer that is not anchored to the substrate.
In another embodiment, the releasing step uses a technique selected from the group consisting of: etching the sacrificial layer, thermally shocking the sacrificial layer, ablating or decomposing by exposure of the sacrificial layer to radiation from a laser source; and decomposing the sacrificial layer by contacting the sacrificial layer with a chemical agent. The functional layer is then optionally removed or retrieved by any means known in the art, such as by a stamp that selectively breaks functional structures from anchors, thereby providing printed functional structures that may correspond to the pattern that was originally applied to the sacrificial layer.
In an embodiment, any of the patterning processes disclosed herein to provide anchors that are incorporated into the multilayer processes of the present invention. For example, the patterning may be applied to one or more release layers of the present invention that separates functional layers to provide additional means for controllably releasing a plurality of functional materials and/or functional layers.
In another embodiment, the invention is a method for fabricating a plurality of transferable semiconductor elements provided in a multilayer array. Such processes provide for manufacture of a large number of elements from a single layer and/or from multiple layers with each layer capable of generating a plurality of elements, as well as providing capability for additional element processing, including processing of elements that are attached to an underlying surface. For example, the method can comprise the steps of providing a wafer having an external surface, such as a wafer comprising an inorganic semiconductor. Selected regions of the external surface are masked by providing a first mask to the external surface, thereby generating masked regions and unmasked regions of the external surface. A plurality of relief features extending from the external surface into the wafer are generated by etching the unmasked regions of the external surface of the wafer. In this manner, at least a portion of the relief features each have at least one contoured side surface having a contour profile that varies spatially along the length of the at least one side. Another masking step, wherein a second mask masks the contoured side surfaces, wherein the contoured side surface is only partially masked by the second mask. This generates masked and unmasked regions provided along the length of the side surfaces. The unmasked regions are etched to generate a plurality of transferable semiconductor elements provided in the multilayer array.
Any of these methods optionally use a wafer that is a bulk semiconductor wafer, for example a silicon wafer having a (111) orientation.
In an aspect, the step of etching the unmasked regions of the external surface of the wafer is carried out by cyclic exposure of the side surfaces of the recessed features to etchants and etch resist materials, such as by cyclic exposure of the side surfaces of the recessed features to reactive ion etchants and etch resist materials. In another aspect, the etching step is carried out using Inductively Coupled Plasma Reactive Ion Etching, Buffered Oxide Etchant or a combination of both Inductively Coupled Plasma Reactive Ion Etching and Buffered Oxide Etchant etching techniques.
In an embodiment, the contour profiles of the contoured side surfaces have a plurality of features extending lengths that intersect a longitudinal axis of the lengths of said side surfaces. For example, the contour profiles may be ridges, ripples and/or scalloped shaped recessed features provided on said side surfaces. Any of the ridges, ripples or scalloped shaped recessed features function as shadow masks during the step of masking the contoured side surfaces by providing the second mask, thereby generating the unmasked regions of the side surfaces.
In an aspect of the invention, the step of masking the contoured side surfaces by providing a second mask is carried out via angled vapor deposition of a mask material.
In an aspect, the step of etching the unmasked regions of side surfaces is carried out via anisotropic etching, such as with a wafer that is a silicon wafer having an (111) orientation, and etching the unmasked regions of the side surfaces is carried out via anisotropic etching preferentially along 110 directions of the silicon wafer. The anisotropic etching is optionally provided by exposing the unmasked regions of said side surface to a strong base.
In an embodiment, the etching of the unmasked regions of the side surfaces generates the transferable semiconductor elements, wherein each of the elements are connected to the wafer via a bridge element.
Any of the systems described optional have a mask that is an etch resistant mask, such as first and second masks that are etch resistant masks.
In another aspect the invention is a method of assembling a plurality transferable semiconductor elements on a substrate by providing a plurality of transferable semiconductor elements by any of the processes disclosed herein and then printing the transferable semiconductor elements on the substrate. For example provided are methods of making an electronic device or component of an electronic device, the method comprising the steps of providing the plurality of transferable semiconductor elements provided in a multilayer array by a process of the present invention. The transferable semiconductor elements are printed on a substrate, thereby making the electronic device or component of the electronic device. Any of the methods disclosed herein use a printing step that is carried out by contact printing. Any of the methods disclosed herein have a printing step that is carried out by sequentially printing transferable semiconductor in different layers of the multilayer.
In an embodiment, the printing semiconductor elements in a first layer of the array expose one or more transferable semiconductor elements in a layer of the array positioned underneath the first layer.
Another embodiment of the present invention is methods of making transferable semiconductor elements by homogeneous and/or heterogeneous anchoring strategies. Such anchoring provides a number of advantages compared to non-anchored systems and processes, such as more efficient use of the wafer that supports the transferable elements, enhanced transfer control and enhanced registered transfer. In particular, the anchors or bridge elements provide localized control over the geometry of elements that are released or transferred.
“Homogeneous anchoring” (e.g.,
“Heterogeneous anchoring” (e.g.,
Any of the anchoring systems are optionally made by patterning one or more of a sacrificial layer, functional layer, and release layer, by any means known in the art to generate exposed wafer substrate and/or exposed underlying semiconductor layer. These anchoring systems are useful for making a plurality of transferable semiconductor elements, as well as for making electronic devices or device components from the transferable semiconductor elements.
Referring to the drawings, like numerals indicate like elements and the same number appearing in more than one drawing refers to the same element. In addition, hereinafter, the following definitions apply:
“Transferable” or “printable” are used interchangeably and relates to materials, structures, device components and/or integrated functional devices that are capable of transfer, assembly, patterning, organizing and/or integrating onto or into substrates. In an embodiment, transferable refers to the direct transfer of a structure or element from one substrate to another substrate, such as from the multilayer structure to a device substrate or a device or component supported by a device substrate. Alternatively, transferable refers to a structure or element that is printed via an intermediate substrate, such as a stamp that lifts-off the structure or element and then subsequently transfers the structure or element to a device substrate or a component that is on a device substrate. In an embodiment, the printing occurs without exposure of the substrate to high temperatures (i.e. at temperatures less than or equal to about 400 degrees Celsius). In one embodiment of the present invention, printable or transferable materials, elements, device components and devices are capable of transfer, assembly, patterning, organizing and/or integrating onto or into substrates via solution printing or dry transfer contact printing. Similarly, “printing” is used broadly to refer to the transfer, assembly, patterning, organizing and/or integrating onto or into substrates, such as a substrate that functions as a stamp or a substrate that is itself a target (e.g., device) substrate. Such a direct transfer printing provides low-cost and relatively simple repeated transfer of a functional top-layer of a multilayer structure to a device substrate. This achieves blanket transfer from, for example, a wafer to a target substrate without the need for a separate stamp substrate. “Target substrate” is used broadly to refer to the desired final substrate that will support the transferred structure. In an embodiment, the target substrate is a device substrate. In an embodiment, the target substrate is a device component or element that is itself supported by a substrate.
“Transferable semiconductor elements” of the present invention comprise semiconductor structures that are able to be assembled and/or integrated onto substrate surfaces, for example by dry transfer contact printing and/or solution printing methods. In one embodiment, transferable semiconductor elements of the present invention are unitary single crystalline, polycrystalline or microcrystalline inorganic semiconductor structures. In this context of this description, a unitary structure is a monolithic element having features that are mechanically connected. Semiconductor elements of the present invention may be undoped or doped, may have a selected spatial distribution of dopants and may be doped with a plurality of different dopant materials, including P and N type dopants. The present invention includes microstructured transferable semiconductor elements having at least one cross sectional dimension greater than or equal to about 1 micron and nanostructured transferable semiconductor elements having at least one cross sectional dimension less than or equal to about 1 micron. Transferable semiconductor elements useful in many applications comprises elements derived from “top down” processing of high purity bulk materials, such as high purity crystalline semiconductor wafers generated using conventional high temperature processing techniques. In one embodiment, transferable semiconductor elements of the present invention comprise composite structures having a semiconductor operational connected to at least one additional device component or structure, such as a conducting layer, dielectric layer, electrode, additional semiconductor structure or any combination of these. In one embodiment, transferable semiconductor elements of the present invention comprise stretchable semiconductor elements and/or heterogeneous semiconductor elements.
“Functional layer” refers to a layer capable of incorporation into a device or device component and that provides at least partial functionality to that device or device component. Depending on the particular device or device component, functional layer has a broad range of compositions. For example, a device that is a solar array can be made from a starting functional layer of III-V micro solar cells, including a functional layer that is itself made up a plurality of distinct layers as provided herein. Release and subsequent printing of such layers provides the basis for constructing a photovoltaic device or device component. In contrast, a functional layer for incorporation into electronics (MESFETs), LEDs, or optical systems may have a different layering configuration and/or compositions. Accordingly, the specific functional layer incorporated into the multilayer structure depends on the final device or device component in which the functional layer will be incorporated.
“Release layer” (sometimes referred to as “sacrificial layer”) refers to a layer that at least partially separates one or more functional layers. A release layer is capable of being removed or providing other means for facilitating separation of the functional layer from other layers of the multi-layer structure, such as by a release layer that physically separates in response to a physical, thermal, chemical and/or electromagnetic stimulation, for example. Accordingly, the actual release layer composition is selected to best match the means by which separation will be provided. Means for separating is by any one or more separating means known in the art, such as by interface failure or by release layer sacrifice. A release layer may itself remain connected to a functional layer, such as a functional layer that remains attached to the remaining portion of the multilayer structure, or a functional layer that is separated from the remaining portion of the multilayer structure. The release layer is optionally subsequently separated and/or removed from the functional layer.
“Supported by a substrate” refers to a structure that is present at least partially on a substrate surface or present at least partially on one or more intermediate structures positioned between the structure and the substrate surface. The term “supported by a substrate” may also refer to structures partially or fully embedded in a substrate.
“Solution printing” is intended to refer to processes whereby one or more structures, such as transferable semiconductor elements, are dispersed into a carrier medium and delivered in a concerted manner to selected regions of a substrate surface. In an exemplary solution printing method, delivery of structures to selected regions of a substrate surface is achieved by methods that are independent of the morphology and/or physical characteristics of the substrate surface undergoing patterning. Solution printing methods useable in the present invention include, but are not limited to, ink jet printing, thermal transfer printing, and capillary action printing.
Useful contact printing methods for assembling, organizing and/or integrating transferable semiconductor elements in the present methods include dry transfer contact printing, microcontact or nanocontact printing, microtransfer or nanotransfer printing and self assembly assisted printing. Use of contact printing is beneficial in the present invention because it allows assembly and integration of a plurality of transferable semiconductor in selected orientations and positions relative to each other. Contact printing in the present invention also enables effective transfer, assembly and integration of diverse classes of materials and structures, including semiconductors (e.g., inorganic semiconductors, single crystalline semiconductors, organic semiconductors, carbon nanomaterials etc.), dielectrics, and conductors. Contact printing methods of the present invention optionally provide high precision registered transfer and assembly of transferable semiconductor elements in preselected positions and spatial orientations relative to one or more device components prepatterned on a device substrate. Contact printing is also compatible with a wide range of substrate types, including conventional rigid or semi-rigid substrates such as glasses, ceramics and metals, and substrates having physical and mechanical properties attractive for specific applications, such as flexible substrates, bendable substrates, shapeable substrates, conformable substrates and/or stretchable substrates. Contact printing assembly of transferable semiconductor structures is compatible, for example, with low temperature processing (e.g., less than or equal to 298K). This attribute allows the present optical systems to be implemented using a range of substrate materials including those that decompose or degrade at high temperatures, such as polymer and plastic substrates. Contact printing transfer, assembly and integration of device elements is also beneficial because it can be implemented via low cost and high-throughput printing techniques and systems, such as roll-to-roll printing and flexographic printing methods and systems. “Contact printing” refers broadly to a dry transfer contact printing such as with a stamp that facilitates transfer of features from a stamp surface to a substrate surface. In an embodiment, the stamp is an elastomeric stamp. Alternatively, the transfer can be directly to a target (e.g., device) substrate. The following references relate to self assembly techniques which may be used in methods of the present invention to transfer, assembly and interconnect transferable semiconductor elements via contact printing and/or solution printing techniques and are incorporated by reference in their entireties herein: (1) “Guided molecular self-assembly: a review of recent efforts”, Jiyun C Huie Smart Mater. Struct. (2003) 12, 264-271; (2) “Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems”, Whang, D.; Jin, S.; Wu, Y.; Lieber, C. M. Nano Lett. (2003) 3(9), 1255-1259; (3) “Directed Assembly of One-Dimensional Nanostructures into Functional Networks”, Yu Huang, Xiangfeng Duan, Qingqiao Wei, and Charles M. Lieber, Science (2001) 291, 630-633; and (4) “Electric-field assisted assembly and alignment of metallic nanowires”, Peter A. Smith et al., Appl. Phys. Lett. (2000) 77(9), 1399-1401.
“Carrier film” refers to a material that facilitates separation of layers. The carrier film may be a layer of material, such as a metal or metal-containing material positioned adjacent to a layer that is desired to be removed. The carrier film may be a composite of materials, including incorporated or attached to a polymeric material or photoresist material, wherein a lift-off force applied to the material provides release of the composite of materials from the underlying layer (such as a functional layer, for example).
“Semiconductor” refers to any material that is a material that is an insulator at a very low temperature, but which has a appreciable electrical conductivity at a temperatures of about 300 Kelvin. In the present description, use of the term semiconductor is intended to be consistent with use of this term in the art of microelectronics and electronic devices. Semiconductors useful in the present invention may comprise element semiconductors, such as silicon, germanium and diamond, and compound semiconductors, such as group IV compound semiconductors such as SiC and SiGe, group III-V semiconductors such as AlSb, AlAs, Aln, AIP, BN, GaSb, GaAs, GaN, GaP, InSb, InAs, InN, and InP, group III-V ternary semiconductors alloys such as AlxGa1-xAs, group II-VI semiconductors such as CsSe, CdS, CdTe, ZnO, ZnSe, ZnS, and ZnTe, group I-VII semiconductors CuCl, group IV-VI semiconductors such as PbS, PbTe and SnS, layer semiconductors such as PbI2, MoS2 and GaSe, oxide semiconductors such as CuO and Cu2O. The term semiconductor includes intrinsic semiconductors and extrinsic semiconductors that are doped with one or more selected materials, including semiconductor having p-type doping materials and n-type doping materials, to provide beneficial electronic properties useful for a given application or device. The term semiconductor includes composite materials comprising a mixture of semiconductors and/or dopants. Specific semiconductor materials useful for in some applications of the present invention include, but are not limited to, Si, Ge, SiC, AIP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GalnAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP. Porous silicon semiconductor materials are useful for applications of the present invention in the field of sensors and light emitting materials, such as light emitting diodes (LEDs) and solid state lasers. Impurities of semiconductor materials are atoms, elements, ions and/or molecules other than the semiconductor material(s) themselves or any dopants provided to the semiconductor material. Impurities are undesirable materials present in semiconductor materials which may negatively impact the electronic properties of semiconductor materials, and include but are not limited to oxygen, carbon, and metals including heavy metals. Heavy metal impurities include, but are not limited to, the group of elements between copper and lead on the periodic table, calcium, sodium, and all ions, compounds and/or complexes thereof.
“Dielectric” and “dielectric material” are used synonymously in the present description and refer to a substance that is highly resistant to flow of electric current. Useful dielectric materials include, but are not limited to, SiO2, Ta2O5, TiO2, ZrO2, Y2O3, Si3N4, STO, BST, PLZT, PMN, and PZT.
“Device field effect mobility” refers to the field effect mobility of an electronic device, such as a transistor, as computed using output current data corresponding to the electronic device.
The invention may be further understood by the following non-limiting examples. All references cited herein are hereby incorporated by reference to the extent not inconsistent with the disclosure herewith. Although the description herein contains many specificities, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of the invention. For example, thus the scope of the invention should be determined by the appended claims and their equivalents, rather than by the examples given.
An aspect of the present invention is providing FMEDs that can be incorporated into a device or device component in a low-cast manner via multi-layer processing. One example of a multilayer structure 10 having a plurality of functional layers (FMEDs) 20 is provided in
Examples of release by different kinds of stimuli include: Release by etching, dissolution, burning, etc. (any means of removal) of an embedded sacrificial layer or sacrificial layers (see Table 1). For example, the release layer(s) may be selectively etched/dissolved/burned/removed two or more times faster than the FMEDs, and/or masking of structures or layers may be employed to protect the FMEDs from exposure to the agent used for removal of the sacrificial layers. The release layer(s) are removed one-at-a-time or two or more sacrificial layers are removed simultaneously.
A structure that is useful for use in MESFETs is provided in
Release of Transferable Structures for Photovoltaics, Electronics and LEDs.
A number of examples of different functional/release layer compositions and geometry for making different devices or device components are provided in
Functional layers are released by any means known in the art, such as by undercutting, etching, dissolution, burning, etc. (any means of removal) of an embedded release layer or sacrificial layer. There are a variety of strategies for releasing functional layers that use a variety of stimuli, some are provided in TABLE 1. TABLE 1 also shows that the composition of the functional and release layers may be selected depending on the release strategy employed. The sacrificial layer(s) are selectively etched/dissolved/burned/removed about two or more times faster than the functional layers that make up the FMEDs. Optionally, a mask layer 400 is provided to protect the FMEDs 20 from exposure to the agent used for removal of the sacrificial layers (see
Simultaneous release of functional layers is outlined in
Release of a single functional layer is outlined in
Any of the released FMEDs may be separated from substrate by stamping or do solvent exchange for fluidic assembly or ink jet printing, electrospinning, etc.
Release is also accomplished by directional etching (e.g. Si 111, Si 110) (see provisional U.S. Pat. App. 60/826,354, filed Sep. 20, 2006 for “Bulk Quantities of Single Crystal Silicon Micro-/Nanoribbons Generated from Bulk Wafers, Atty. ref. no. 151-06P, hereby incorporated by reference to the extent not inconsistent herewith) for anisotropic etching and/or mask layer to protect FMEDs from the etching.EXAMPLE 2
Release of Transferable Structures by Laser Ablation.
Other release methods include release by removal of the mother substrate by grinding/polishing/etching or release by thermal shock (e.g. by thermal expansion coefficient mismatch). Release may also be by ablation/decomposition/chemical reaction of embedded layers, such as ablation/decomposition/chemical reaction caused by laser-induced heating.
Release of Transferable Structures by Propagation of an Induced Interfacial Crack.
Another release mechanism is by introducing a crack at an interface between FMEDs and the mother substrate and then pulling the FMEDs away from the mother substrate (e.g. using a rubber stamp) to propagate the crack (see
Optionally, any of the above means for releasing a transferable structure is combined with a carrier structure, for example a carrier film (
Release by any of the methods described herein is optionally incorporated into a process that reuses the mother substrate 40, as shown in
The processes disclosed herein are particularly suited for high-throughput printing of structures from a multilayer device to a substrate or component supported by a substrate, thereby decreasing manufacturing time and costs. For example,
Bulk Quantities of Single-Crystal Silicon Micro-/Nanoribbons Generated from Bulk Wafers.
This Example demonstrates a strategy for producing bulk quantities of high quality, dimensionally uniform single-crystal silicon micro- and nanoribbons from bulk silicon (111) wafers. The process uses etched trenches with controlled rippled structures defined on the sidewalls, together with angled evaporation of masking materials and anisotropic wet etching of the silicon, to produce multilayer stacks of ribbons with uniform thicknesses and lithographically defined lengths and widths, across the entire surface of the wafer. Ribbons with thicknesses between tens and hundreds of nanometers, widths in the micrometer range, and lengths of up to several centimeters, are produced, in bulk quantities, using this approach. Printing processes enable the layer by layer transfer of organized arrays of such ribbons to a range of other substrates. Good electrical properties (mobilities ˜190 cm2V−1s−1, on/off >104) can be achieved with these ribbons in thin film type transistors formed on plastic substrates, thereby demonstrating one potential area of application.
Nanostructured elements of single-crystal silicon, in the form of wires, ribbons, and particles, are of interest for a number of applications in electronics, optoelectronics, sensing, and other areas. The ribbon geometry is important for certain devices because it provides, for example, large planar surfaces for chemical sensing and photodetection, and geometries that can efficiently fill the channel regions of transistors. Growth techniques related to the well-developed chemical synthetic approaches used for silicon nanowiresl have been adapted and applied with some success to produce Si nanoribbons.2The levels of dimensional control and yields of ribbons provided by these procedures and similar ones for materials such as oxides (ZnO, SnO2, Ga2O3, Fe2O3, In2O3, CdO, PbO2, etc.),3 sulfides (CdS, ZnS),4 nitride (GaN),5 and selenides (CdSe, ZnSe, Sb2Se3)6 are, however, modest. By contrast, approaches that rely on the lithographic processing of top surfaces of semiconductor wafers enable well-controlled thicknesses, widths, lengths, crystallinity, and doping levels. These methods can form membranes, tubes, and ribbons, with thicknesses in the micrometer to nanometer range, composed of Si, SiGe, bilayered Si/SiGe, GaAs, GaN, and others.7-12Furthermore, various processes can transfer these elements, in organized arrays, to other substrates for device integration. This “top down” approach has three main disadvantages compared to the growth techniques. First, elements with widths less than ˜100 nm are difficult to fabricate, due to practical limitations in the lithography. Second, only those materials that can be grown in thin film or bulk wafer form can be used. Third, and most significant for many applications, the production of bulk quantities of micro-/nanostructures requires large numbers of wafers, each of which can be expensive. The first disadvantage is irrelevant to the many applications that do not require structures with such small dimensions. The second does not, of course, apply to many important materials, including silicon. This Example presents results that address the third limitation. In particular, it introduces a simple method for generating large numbers of high-quality Si ribbons, with thicknesses down to tens of nanometers, from standard bulk Si wafers, in a single processing sequence. Briefly, the approach begins with controlled deep reactive ion etching of silicon wafers through an etch mask to produce trenches with well-defined rippled sidewall morphologies. A collimated flux of metal deposited at an angle onto these ripples creates isolated metal lines that act as masks for highly anisotropic wet etching of the silicon along planes parallel to the surface of the wafer. This single etching step creates bulk quantities of silicon ribbons in multilayer stacked geometries. These ribbons can be removed from the wafer and solution cast or dry transfer printed onto desired substrates, with or without preserving their lithographically defined spatial order, for integration into devices such as transistors. This approach relies only on standard cleanroom processing equipment. As a result, it can be useful to researchers with interest in silicon micro-nanostructures but without the specialized growth chambers and recipes needed to create them in large quantities using direct synthetic techniques.
To facilitate integration of these elements into devices, it is valuable to maintain their lithographically defined alignments and positions. For this purpose, we introduced breaks (width=10-20 μm) in the SiO2lines such that the ends of each ribbon remain anchored to the Si wafer even after complete undercut etching with KOH. Soft printing techniques that use elastomeric elements of poly(dimethylsiloxane) (PDMS) can lift up organized arrays of such anchored Si ribbons,7,15one layer at a time, from the source wafer for transfer to a target substrate.
Technologies) with a thin, spin cast adhesive layer (thickness=135 nm, SU-8, Microchem) and heating at 70° C. for 1 min produced strong bonding between the ribbons and the substrate. Peeling away the PDMS removed the ribbons from the PDMS. Flood exposing the adhesive (photopolymer) layer to ultraviolet light (λ=365 nm, 13 mW/cm2, 10 s) and further heating (120° C., 5 min) enhanced the adhesion between the ribbons and the substrate. Multiple cycles of transfer printing with a single wafer source of ribbons can produce large area coverage (compared to the wafer) on plastic, as illustrated in
The high level of disorder present in the ribbons shown in
The anchoring approach illustrated in
To demonstrate one possible use of printed ribbon arrays in electronics, we fabricated field effect transistors (
In summary, this Example demonstrates a simple fabrication strategy for producing bulk quantities of single-crystal silicon micro-/nanoribbons from bulk silicon (111) wafers. Each layer in the multilayer stacks produced by this approach can be separately transfer printed onto other substrates, for integration into devices such as transistors. The simplicity of the procedures, the ability to form organized arrays for devices, the high quality of the materials, and the potential for other device possibilities such as sensors, photodetectors and perhaps photovoltaics, in addition to electronic circuits, suggest potential value for this type of approach to silicon ribbons.
Photomicrographs of various sidewalls according to different STS-ICPRIE conditions and silicon nanoribbons with different thicknesses, the extent of shadowing mask vs angles for electron beam evaporation, and seven-layered Si ribbons and spectra from a EDAX energy dispersive spectroscopy (EDS) study are provided in
(1) (a) Wagner, R. S.; Ellis, W. C. Appl. Phys. Lett. 1964, 4, 89. (b) Holmes, J. D.; Johnston, K. P.; Doty, R. C.; Korgel, B. A. Science 2000, 287, 1471. (c) Yu, J.-Y.; Chung, S.-W.; Heath, J. R. J. Phys. Chem. B 2000, 104, 11864. (d) Wu, Y.; Yang, P. J. Am. Chem. Soc. 2001, 123, 3165. (e) Wu, Y.; Fan, R.; Yang, P. Nano Lett. 2002, 2, 83. (f) Shi, W.-S.; Peng, H.-Y.; Zheng, Y.-F.; Wang, N.; Shang, N.-G.; Pan, Z.-W.; Lee, C.-S.; Lee, S.-T. AdV. Mater. 2000, 12, 1343. (g) Wu, Y.; Xiang, J.; Yang, C.; Lu, W.; Lieber, C. M. Nature 2004, 430, 61. (h) Lu, W.; Xiang, J.; Timko, B. P.; Wu, Y.; Lieber, C. M. Proc. Natl. Acad. Sci. U.S.A. 2005, 102, 10046. (i) Xiang, J.; Lu, W.; Hu, Y.; Wu, Y.; Yan, H.; Lieber, C. M. Nature 2006, 441, 489.
(2) (a) Shi, W.; Peng H.; Wang, N.; Li, C. P.; Xu, L.; Lee, C. S.; Kalish, R.; Lee, S.-T. J. Am. Chem. Soc. 2001, 123, 11095. (b) Zhang, R.-Q.; Lifshitz, Y.; Lee, S.-T. AdV. Mater. 2003, 15, 635. (c) Shan, Y.; Kalkan, A. K.; Peng, C.-Y.; Fonash, S. J. Nano Lett. 2004, 4, 2085.
(3) (a) Pan, Z. W.; Dai, Z. R.; Wang, Z. L. Science 2001, 291, 1947. (b) Li, Y.
B.; Bando, Y.; Sato, T.; Kurashima, K. Appl. Phys. Lett. 2002, 81, 144. (c) Arnold, M. S.; Avouris, P.; Pan, Z. W.; Wang, Z. L. J Phys. Chem. B 2003, 107, 659. (d) Dai, Z. R.; Pan, Z. W.; Wang, Z. L. J. Phys. Chem. B 2002, 106, 902. (e) Wen, X.; Wang, S.; Ding, Y.; Wang, Z. L.; Yang, S. J. Phys. Chem. B 2005, 109, 215. (f) Kong, X. Y.; Wang, Z. L. Solid State Commun. 2003, 128, 1.
(4) (a) Kar, S.; Satpati, B.; Satyam, P. V.; Chaudhuri, S. J. Phys. Chem. B 2005, 109, 19134. (b) Kar, S.; Chaudhuri, S. J Phys. Chem. B 2006, 110, 4542. (c) Kar, S.; Chaudhuri, S. J. Phys. Chem. B 2005, 109, 3298. (d) Li, Y.; Zou, K.; Shan, Y. Y.; Zapien, J. A.; Lee, S.-T. J. Phys. Chem. B 2006, 110, 6759. (e) Zhang, Z.; Wang, J.; Yuan, H.; Gao, Y.; Liu, D.; Song, L.; Xiang, Y.; Zhao, X.; Liu, L.; Luo, S.; Dou, X.; Mou, S.; Zhou, W.; Xie, S. J Phys. Chem. B 2005, 109, 18352. (f) Wang, Z. Q.; Gong, J. F.; Duan, J. H.; Huang, H. B.; Yang, S. G.; Zhao, X. N.; Zhang, R.; Du, Y. W. Appl. Phys. Lett. 2006, 89, 033102.
(5) Bae, S. Y.; Seo, H. W.; Park, J.; Yang, H.; Park, J. C.; Lee, S. Y. Appl. Phys. Lett. 2002, 81, 126.
(6) (a) Ma, C.; Ding, Y.; Moore, D.; Wang, X.; Wang, Z. L. J. Am. Chem. Soc. 2004, 126, 708. (b) Ding, Y.; Ma, C.; Wang, Z. L. AdV. Mater. 2004, 16, 1740. (c) Joo, J.; Son, J. S.; Kwon, S. G.; Yu, J. H.; Hyeon, T. J. Am. Chem. Soc. 2006, 128, 5632. (d) Zhang, X. T.; Ip, K. M.; Liu, Z.; Leung, Y. P.; Li, Q.; Hark, S. K. Appl. Phys. Lett. 2004, 84, 2641. (e) Xie, Q.; Liu, Z.; Shao, M.; Kong, L.; Yu, W.; Qian, Y. J. Cryst. Growth 2003, 252, 570.
(7) (a) Menard, E.; Lee, K. J.; Khang, D.-Y.; Nuzzo, R. G.; Rogers, J. A. Appl. Phys. Lett. 2004, 84, 5398. (b) Menard, E.; Nuzzo, R. G.; Rogers, J. A. Appl. Phys. Lett. 2005, 86, 093507. (c) Zhu, Z.-T.; Menard, E.; Hurley, K.; Nuzzo, R. G.; Rogers, J. A. Appl. Phys. Lett. 2005, 86, 133507. (d) Khang, D.-Y.; Jiang, H.; Huang, Y.; Rogers, J. A. Science 2006, 311, 208. (e) Sun, Y.; Kumar, V.; Adesida, I.; Rogers, J. A. AdV. Mater. 2006, in press.
(8) (a) Zhang, P.; Tevaarwerk, E.; Park, B.-N.; Savage, D. E.; Geller, G. K.; Knezevic, I.; Evans, P. G.; Eriksson, M. A.; Lagally, M. G. Nature 2006, 439, 703. (b) Roberts, M. M.; Klein, L. J.; Savage, D. E.; Slinker, K. A.; Friesen, M.; Geller, G.; Eriksson, M. A.; Lagally, M. G. Nat. Mater. 2006, 5, 388.
(9) (a) Huang, M.; Boone, C.; Roberts, M.; Savage, D. E.; Lagally, M. G.; Shaji, N.; Qin, H.; Blick, R.; Nairn, J. A.; Liu, F. AdV. Mater. 2005, 17, 2860. (b) Zhang, L.; Ruh, E.; Grutzmacher, D.; Dong, L.; Bell, D. J.; Nelson, B. J.; Schönenberger, C. Nano Lett. 2006, 6, 1311.
(10) (a) Desai, T. A.; Hansford, D. J.; Kulinsky, L.; Nashat, A. H.; Rasi, G.; Tu, J.; Wang, Y.; Zhang, M.; Ferrari, M. Biomed. MicrodeVices 1999, 2, 11. (b) Bhushan, B.; Kasai, T.; Nguyen, C. V.; Meyyappan, M. Microsyst. Technol. 2004, 10, 633.
(11) Mack, S.; Meitl, M. A.; Baca, A. J.; Zhu, Z.-T.; Rogers, J. A. Appl. Phys. Lett. 2006, 88, 213101.
(12) (a) Létant, S. E.; Hart, B. R.; Van Buuren, A. W.; Terminello, L. J. Nat. Mater. 2003, 2, 391. (b) Storm, A. J.; Chen, J. H.; Ling, X. S.; Zandbergen, H. W.; Dekker, C. Nat. Mater. 2003, 2, 537.
(13) (a) Gmbh, R. B. U.S. Pat. No. 4,855,017, U.S. Pat. No. 4,784,720, German Patent 4241045C1, 1994. (b) Ayo'n, A. A.; Braff, R.; Lin, C. C.; Sawin, H. H.; Schmidt, M. A. J. Electrochem. Soc. 1999, 146, 339. (c) Chen, K.-S.; Ayo'n, A. A. J. Microelectromech. Syst. 2002, 11, 264.
(14) (a) Madou, M. Fundamentals of Microfabrication; CRC Press LLC: Boca Raton, Fla., 1997; pp 177-187. (b) Chou, B. C. S.; Chen C.-N.; Shie, J.-S. Sens. Actuators, A 1999, 75, 271. (c) Lee, S.; Park, S.; Cho D. J. Microelectromech. Syst. 1999, 8, 409. (d) Ensell, G. J. Micromech. Microeng. 1995, 5, 1. (e) Kandall, D. L. Annu. ReV. Mater. Sci. 1979, 9, 373.
(15) Meitl, M. A.; Zhu, Z.-T.; Kumar, V.; Lee, K. J.; Feng, X.; Huang, Y. Y.; Adesida, I.; Nuzzo, R. G.; Rogers, J. A. Nat. Mater. 2006, 5, 33.
(16) Garcia, S. P.; Bao, H.; Hines, M. A. Phys. ReV. Lett. 2004, 93, 166102.
(17) (a) Streetman, B. G.; Banerjee, S. Solid State Electronic Devices, 5th ed.; Prentice Hall: Upper Saddle River, N.J., 2000; pp 274-275. (b) Razouk, R. R.; Deal, B. E. J. Electrochem. Soc. 1979, 126, 1573. (c) Kato, Y.; Takao, H.; Sawada, K.; Ishida, M. Jpn. J. Appl. Phys. 2004, 43, 6848.
U.S. patent application Ser. Nos. 11/115,954, now U.S. Pat. No. 7,195,733; 11/145,574, now U.S. Pat. No. 7,622,367; 11/145,542, now U.S. Pat. No. 7,557,367; 60/863,248, 11/465,317, 11/423,287, now U.S. Pat. No. 7,521,292; 11/423,192, now U.S. Pat. No. 7,943,491; and 11/421,654, now U.S. Pat. No. 7,799,699 are hereby incorporated by reference to the extent not inconsistent with the present description.
All references throughout this application, for example patent documents including issued or granted patents or equivalents; patent application publications; unpublished patent applications; and non-patent literature documents or other source material; are hereby incorporated by reference herein in their entireties, as though individually incorporated by reference, to the extent each reference is at least partially not inconsistent with the disclosure in this application (for example, a reference that is partially inconsistent is incorporated by reference except for the partially inconsistent portion of the reference).
Where the terms “comprise”, “comprises”, “comprised”, or “comprising” are used herein, they are to be interpreted as specifying the presence of the stated features, integers, steps, or components referred to, but not to preclude the presence or addition of one or more other feature, integer, step, component, or group thereof. Separate embodiments of the invention are also intended to be encompassed wherein the terms “comprising” or “comprise(s)” or “comprised” are optionally replaced with the terms, analogous in grammar, e.g.; “consisting/consist(s)” or “consisting essentially of/consist(s) essentially of” to thereby describe further embodiments that are not necessarily coextensive.
The invention has been described with reference to various specific and preferred embodiments and techniques. However, it should be understood that many variations and modifications may be made while remaining within the spirit and scope of the invention. It will be apparent to one of ordinary skill in the art that compositions, methods, devices, device elements, materials, procedures and techniques other than those specifically described herein can be applied to the practice of the invention as broadly disclosed herein without resort to undue experimentation. All art-known functional equivalents of compositions, methods, devices, device elements, materials, procedures and techniques described herein are intended to be encompassed by this invention. Whenever a range is disclosed, all subranges and individual values are intended to be encompassed as if separately set forth. This invention is not to be limited by the embodiments disclosed, including any shown in the drawings or exemplified in the specification, which are given by way of example or illustration and not of limitation. The scope of the invention shall be limited only by the claims.
1. A method of making transferable semiconductor structures, said method comprising the steps of:
- providing a multilayer structure comprising a plurality of functional layers and a plurality of release layers; wherein said release layers are positioned between functional layers in said multilayer structure, and said functional layers include a plurality of semiconductor structures; and
- releasing at least a portion of said semiconductor structures from said multilayer structure by separating one or more of said release layers from one or more of said functional layers, thereby generating said transferable semiconductor structures.
2. The method of claim 1, wherein said plurality of semiconductor structures comprises a semiconductor device.
3. The method of claim 2, wherein said semiconductor device is selected from the group consisting of: a P-N junction, a thin film transistor, a single junction solar cell, a multi-junction solar cell, a photodiode, a light emitting diode, a laser, a CMOS device, a MOSFET device, a MESFET device, and a HEMT device.
4. The method of claim 1, wherein said semiconductor structures comprise a plurality of semiconductor thin films.
5. The method of claim 4, wherein each of said semiconductor thin films is a single crystalline semiconductor layer.
6. The method of claim 4, wherein each of said semiconductor thin films is selected from the group consisting of: an organic semiconductor layer, an inorganic semiconductor layer, a III-V semiconductor layer; and a group IV elemental or compound semiconductor.
7. The method of claim 4, wherein said plurality of semiconductor thin films comprise at least two semiconductor thin films having different semiconductor materials or dopants.
8. The method of claim 1, wherein said semiconductor structures comprise a doped semiconductor layer.
9. The method of claim 8, wherein said doped semiconductor layer forms part of a P-N junction.
10. The method of claim 1, wherein said semiconductor structures comprise a solar cell.
11. The method of claim 1, wherein said semiconductor structures comprise material selected from the group consisting of:
- Si, Ge, SiC, AIP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GalnAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP.
12. The method of claim 1, wherein said functional layer further comprises a dielectric layer, an electrode or conducting layer.
13. The method of claim 1, wherein each plurality of semiconductor structures has a thickness selected from a range that is greater than 5 nm and less than 50,000 nm.
14. The method of claim 1, wherein said multilayer structure has a functional layer number that is greater than or equal to 2 and less than or equal to 200, and a release layer number that is greater than or equal to 2 and less than or equal to 200.
15. The method of claim 1 further comprising the step of generating said multilayer structure on a substrate, wherein at least one release layer is provided between said functional layers and said substrate.
16. The method of claim 15 further comprising the step of repeating said steps of generating said multilayer structure on a substrate and releasing at least a portion of said semiconductor structures from said multilayer structure; wherein said substrate is reused during said step of repeating said steps of generating said multilayer structure on a substrate and releasing at least a portion of said semiconductor structures from said multilayer structure.
17. The method of claim 1, wherein said plurality of semiconductor structures comprise:
- III-V semiconductor epilayers, wherein at least two semiconductor epilayers have different semiconductor materials.
18. The method of claim 17, wherein said III-V semiconductor epilayers comprises:
- a p-doped GaAs top layer;
- a low-doped GaAs middle layer; and
- an n-doped GaAs lower layer supported by said release layer.
19. The method of claim 17, wherein said release layer comprises Al0.9Ga0.1As.
20. The method of claim 1 for making photovoltaics, wherein said semiconductor structures comprise:
- a first layer of n-doped GaAs supported by said release layer;
- a second layer supported by said first layer, said second layer comprising a back-surface field or Bragg-reflector layer;
- a third layer comprising a n-doped GaAs base layer supported by said second layer;
- a fourth layer comprising a p-doped GaAs emitter;
- a fifth layer comprising a p-doped In0.49Ga0.51P passivation layer supported by said fourth layer; and
- a sixth layer comprising a p-doped GaAs layer supported by said fifth layer.
21. The method of claim 20, further comprising a buffer layer positioned between said first and second layer, wherein said buffer layer comprises n-doped GaAs.
22. The method of claim 20, wherein said release layer comprises a layer of Al0.96Ga0.04As of sufficient thickness to avoid sagging of said multilayer.
23. The method of claim 22, wherein said release layer thickness is greater than or equal to 300 nm and less than or equal to 2500 nm.
24. The method of claim 20, wherein said plurality of functional layers are selected from a range that is greater than or equal to 2 and less than or equal to 200.
25. The method of claim 1, further comprising providing said multilayer structure on a GaAs substrate.
26. The method of claim 25, wherein each functional layer comprises an n-doped GaAs layer and a semi-insulating layer of AlGaAs.
27. The method of claim 26, wherein said release layer is Al0.96Ga0.04As.
28. The method of claim 26, wherein the number of said functional layers is greater than or equal to 2 and less than or equal to 200.
29. The method of claim 1, wherein each functional layer comprises 15 stacked layers arranged from a top-most layer 1 to a bottom-most layer 15 supported by said release layer, and said stacked layers comprise:
- 1 GaAs:C
- 2 Al0.45Ga0.55As:C
- 3 Al0.5In0.5P:Mg
- 4 Al0.25Ga0.25In0.5P
- 5 Ga0.44In0.56P
- 6 Al0.25Ga0.25In0.5P
- 7 Ga0.44In0.56P
- 8 Al0.25Ga0.25In0.5P
- 9 Ga0.44In0.56P
- 10 Al0.25Ga0.25In0.5P
- 11 Ga0.44In0.56P
- 12 Al0.25Ga0.25In0.5P
- 13 Al0.5In0.5P
- 14 Al0.45Ga0.55As:Te
- 15 GaAs:Te.
30. The method of claim 29, wherein said release layer comprises Al0.96Ga0.04As and said multilayer structure is supported by a GaAs substrate.
31. A multi-layer stack system for providing transferable structures, said multi-layer stack system comprising:
- a substrate;
- a release layer that covers at least a portion of said substrate;
- a plurality of functional layers supported by said release layer and said substrate, wherein adjacent functional layers are separated by a release layer positioned between adjacent functional layers;
- wherein said functional layers comprise a plurality of semiconductor structures.
32. The multi-layer stack system of claim 31, wherein said semiconductor structures comprise a semiconductor thin film.
33. The multi-layer stack of claim 32, wherein said semiconductor thin film is a doped semiconductor layer.
34. The multi-layer stack of claim 31, wherein said plurality of semiconductor structures comprise a semiconductor device.
35. The multi-layer stack of claim 34, wherein said semiconductor device is selected from the group consisting of a P-N junction, a thin film transistor, a single junction solar cell, a multi-junction solar cell, a photodiode, a light emitting diode, a laser, a CMOS device, a MOSFET device, a MESFET device, and a HEMT device.
36. The multi-layer stack system of claim 31, wherein said semiconductor structures comprise a plurality of semiconductor thin films.
37. The multi-layer stack system of claim 36, wherein said plurality of semiconductor thin films comprise:
- a top layer of p-doped GaAs;
- a middle layer of low-doped GaAs; and
- and a bottom layer of n-doped GaAs.
38. The multi-layer stack system of claim 36, wherein said plurality of semiconductor thin films comprise a layer of n-doped GaAs supported by a semi-insulative layer of AlGaAs.
39. The multi-layer stack system of claim 36, wherein said plurality of semiconductor thin films comprise: p-doped GaAs, In0.49Ga0.51P and a back-surface field or Bragg-reflector layer.
40. The multi-layer stack system of claim 31, wherein said substrate comprises GaAs and said release layer comprises aluminum gallium arsenide.
41. The multi-layer stack system of claim 40, wherein said release layer comprises Al0.96Ga0.04As.
42. The multi-layer stack system of claim 36, wherein said plurality of semiconductor thin films are independently selected from the group consisting of: GaAs; InP; AlxGa1-xAs, with x<0.5; InGaAlAsP with AlAs≦50%; C; Si; Ge; SiC; SiGe; Au; Ag; Cu; Pd; Pt; InGaAlN; In1-yGayAsxP1-x, x, y≦0.05; and AlxGa1-xAs, x≧0.9.
43. The multi-layer stack system of claim 31, wherein said release layer is selected from the group consisting of:
- AlGa1-xAs, where x≧0.7;
- an organic polymer;
- GaAs1-xNy, where y<x<1;
- InGaAs; and
Filed: Sep 8, 2011
Publication Date: Dec 29, 2011
Applicant: The Board of Trustees of the University of Illinois (Urbana, IL)
Inventors: John A. ROGERS (Champaign, IL), Ralph G. NUZZO (Champaign, IL), Matthew MEITL (Raleigh, NC), Heung Cho KO (Urbana, IL), Jongseung YOON (Urbana, IL), Etienne MENARD (Durham, NC), Alfred J. BACA (Urbana, IL)
Application Number: 13/228,041