High voltage multigate device and manufacturing method thereof
The present invention discloses a high voltage multigate device and a manufacturing method thereof. The high voltage multigate device includes: a semiconductor fin doped with first conductive type impurities; a dielectric layer, which overlays a portion of the semiconductor fin; a gate which overlays the dielectric layer; a drain doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin; a source doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and a drift region or a well doped with second conductive type impurities, which is formed in the semiconductor fin at least between the drain and the gate.
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The present invention claims priority to TW 100103418, filed on Jan. 28, 2011.
BACKGROUND OF THE INVENTION1. Field of Invention
The present invention relates to a high voltage multigate device and its manufacturing method.
2. Description of Related Art
In device characteristics with respect to gate control, that is, device characteristics with respect to device on/off behavior, the three high voltage devices mentioned above require a better design to reduce their conduction resistance and leakage current.
In the view of above, to overcome the drawback in the prior art, the present invention proposes a high voltage multigate device and its manufacturing method to improve the device characteristics so that the device provides a broader range of applications.
SUMMARY OF THE INVENTIONThe objective of the present invention is to provide a high voltage multigate device and its manufacturing method.
To achieve the foregoing objective, in one perspective of the present invention, it provides a high voltage multigate device comprising: a semiconductor fin doped with first conductive type impurities; a dielectric layer overlaying a portion of the semiconductor fin; a gate overlaying the dielectric layer; a drain doped with second conductive type impurities, the drain being formed in the semiconductor fin or coupled to the semiconductor fin; a source doped with second conductive type impurities, the source being formed in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and a first drift region or a well doped with second conductive type impurities, the first drift region or the well being formed in the semiconductor fin at least between the drain and the gate.
In another perspective of the present invention, it provides a method for manufacturing a high voltage multigate device, comprising: forming a semiconductor fin doped with first conductive type impurities; forming a dielectric layer overlaying a portion of the semiconductor fin; forming a gate overlaying the dielectric layer; forming a drain doped with second conductive type impurities in the semiconductor fin or coupled to the semiconductor fin; forming a source doped with second conductive type impurities in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and forming a first drift region or a well doped with second conductive type impurities in the semiconductor fin at least between the drain and the gate.
The foregoing high voltage multigate device may be a planar device or a vertical device, that is, the source and the drain may be located on the same plane or on different planes.
The foregoing high voltage multigate device may be a symmetric or asymmetric device. When the high voltage multigate device is a symmetric device, it further includes a second drift region with second conductive type impurities, the second drift region being formed in the semiconductor fin at least between the source and the gate.
The objectives, technical details, features, and effects of the present invention will be better understood with regard to the detailed description of the embodiments below, with reference to the drawings.
The drawings as referred to throughout the description of the present invention are for illustration only, to show the interrelations between the layers/parts, but not drawn according to actual scale.
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The DDDMOS devices of the third to sixth embodiments have better device characteristics compared to the prior art device shown in
The DMOS devices of the seventh and eighth embodiments have better device characteristics compared to the prior art device shown in
The present invention has been described in considerable detail with reference to certain preferred embodiments thereof. It should be understood that the description is for illustrative purpose, not for limiting the scope of the present invention. Those skilled in this art can readily conceive variations and modifications within the spirit of the present invention. For example, other manufacturing process steps or structures which do not affect the characteristics of the devices, such as a deep-well region, etc., can be added. As another example, the lithography is not limited to photolithography; it can be electron beam lithography, X-ray lithography or other methods. As yet another example, the present invention also can be applied to other types of multigate devices, such as a gate with a drum-shaped structure. Thus, the present invention should cover all such and other modifications and variations, which should be interpreted to fall within the scope of the following claims and their equivalents.
Claims
1. A high voltage multigate device, comprising:
- a semiconductor fin doped with first conductive type impurities;
- a dielectric layer overlaying a portion of the semiconductor fin;
- a gate overlaying the dielectric layer;
- a drain doped with second conductive type impurities, the drain being formed in the semiconductor fin or coupled to the semiconductor fin;
- a source doped with second conductive type impurities, the source being formed in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and
- a first drift region or a well doped with second conductive type impurities, the first drift region or the well being formed in the semiconductor fin at least between the drain and the gate.
2. The high voltage multigate device of claim 1, further comprising a body region doped with first conductive type impurities, surrounding the source and separating the source and the gate.
3. The high voltage multigate device of claim 1, wherein the gate includes multiple separated gate plates.
4. The high voltage multigate device of claim 1, further comprising an isolation structure formed in the semiconductor fin, partially or totally in a region surrounded by the gate.
5. The high voltage multigate device of claim 1, further comprising a second drift region with second conductive type impurities, the second drift region being formed in the semiconductor fin at least between the source and the gate.
6. The high voltage multigate device of claim 1, wherein the source and the drain are located on the same plane or on different planes.
7. A method for manufacturing a high voltage multigate device, comprising:
- forming a semiconductor fin doped with first conductive type impurities;
- forming a dielectric layer overlaying a portion of the semiconductor fin;
- forming a gate overlaying the dielectric layer;
- forming a drain doped with second conductive type impurities in the semiconductor fin or coupled to the semiconductor fin;
- forming a source doped with second conductive type impurities in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and
- forming a first drift region or a well doped with second conductive type impurities in the semiconductor fin at least between the drain and the gate.
8. The method of claim 7, further comprising: forming a body region doped with first conductive type impurities, surrounding the source and separating the source and the gate.
9. The method of claim 7, wherein the gate includes multiple separated gate plates.
10. The method of claim 7, further comprising: forming an isolation structure in the semiconductor fin partially or totally in a region surrounded by the gate.
11. The method of claim 7, further comprising: forming a drift region with second conductive type impurities, the drift region being formed in the semiconductor fin at least between the source and the gate.
12. The method of claim 7, wherein the source and the drain are located on the same plane or on different planes.
Type: Application
Filed: Mar 24, 2011
Publication Date: Aug 2, 2012
Applicant:
Inventors: Tsung-Yi Huang (Hsinchu City), Chien-Wei Chiu (Beigang Township)
Application Number: 13/065,569
International Classification: H01L 29/78 (20060101); H01L 21/336 (20060101);