With Channel Containing Layer Contacting Drain Drift Region (e.g., Dmos Transistor) (epo) Patents (Class 257/E29.256)
  • Patent number: 9041103
    Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC
    Inventors: Won Gi Min, Zhihong Zhang, Hongzhong Xu, Jiang-Kai Zuo
  • Patent number: 9041104
    Abstract: A memory includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. A first channel region of a first conductivity type is provided on a surface of the semiconductor layer below the gate insulating film. A diffusion layer of a second conductivity type is provided below the first channel region in the semiconductor layer. The diffusion layer contacts a bottom of the first channel region in a direction substantially vertical to a surface of the semiconductor layer. The diffusion layer forms a PN junction with the bottom of the first channel region. A drain of a first conductivity type and a source of a second conductivity type are provided on a side and another side of the first channel region. A sidewall film covers a side surface of the first channel region on a side of the diffusion layer.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Emiko Sugizaki, Shigeru Kawanaka, Kanna Adachi
  • Patent number: 9018703
    Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: April 28, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Patent number: 9018710
    Abstract: A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region. A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seung-Mi Lee, Yun-Hyuck Ji
  • Patent number: 9012289
    Abstract: A semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises a gate, and source and drain regions on opposite sides of the gate, wherein a portion of a gate dielectric layer located above the channel region is thinner than a portion of the gate dielectric layer located at the overlap region of the drain and the gate. The thicker first thickness portion may ensure that the device can endure a higher voltage at the drain to gate region, while the thinner second thickness portion may ensure excellent performance of the device.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jinhua Liu
  • Patent number: 9012984
    Abstract: A transistor device includes a drift layer having a first conductivity type, a body layer on the drift layer, the body layer having a second conductivity type opposite the first conductivity type, and a source region on the body layer, the source region having the first conductivity type. The device further includes a trench extending through the source region and the body layer and into the drift layer, a channel layer on the inner sidewall of the trench, the channel layer having the second conductivity type and having an inner sidewall opposite an inner sidewall of the trench, a gate insulator on the inner sidewall of the channel layer, and a gate contact on the gate insulator.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 21, 2015
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant Agarwal, John Palmour
  • Patent number: 9006819
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: April 14, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Akihiko Furukawa, Yukiyasu Nakao, Masayuki Imaizumi
  • Patent number: 9000519
    Abstract: An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 9000520
    Abstract: A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
  • Patent number: 9000516
    Abstract: A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 7, 2015
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Shengan Xiao
  • Patent number: 8994113
    Abstract: A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A lateral isolation layer is disposed in the isolation trench. The semiconductor device further includes a source region and a drain region, and a body region and a drift region disposed between the source region and the drain region. The semiconductor device additionally includes a gate electrode adjacent to at least a portion of the body region and a field plate adjacent to at least a portion of the drift region. A field dielectric layer is disposed between the drift region and the field plate. A top surface of the field dielectric layer is disposed at a greater height measured from a first main surface of the semiconductor substrate than a top surface of the lateral isolation layer.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Marc Strasser, Karl-Heinz Gebhardt, Andreas Meiser, Till Schloesser
  • Patent number: 8987818
    Abstract: A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region of the substrate, and a second portion forming a polysilicon field plate formed over a portion of a transition region of the substrate. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap, thereby forming a bridge having the same doping type as the substrate body. The field plate also extends over a field oxide filled trench formed in the substrate. The field plate is electrically coupled to a source of the split gate power transistor.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Joel Montgomery McGregor, Vishnu Khemka
  • Patent number: 8987820
    Abstract: A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region disposed in a portion of the well region from a first side; a second doped region disposed in the well region from a second side; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a first trench in the third doped region, the first doped region, the well region, and the substrate adjacent to the first surface; a conductive contact in the first trench; a second trench in the substrate adjacent to the second surface; a first conductive layer in second trench; and a second conductive layer over the second surface of the substrate and the first conductive layer.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: March 24, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang
  • Patent number: 8981475
    Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region and partially overlaps the drift region. A conformal dielectric layer is on the top surface and forms a mesa above the gate conductor. The conformal dielectric layer has a conformal etch-stop layer embedded therein. Contact studs extend through the dielectric layer and the etch-stop layer, and are connected to the source region, drain region, and gate conductor. A source electrode contacts the source contact stud, a gate electrode contacts the gate contact stud, and a drain electrode contacts the drain contact stud. A drift electrode is over the drift region.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Santosh Sharma, Yun Shi, Anthony K. Stamper
  • Patent number: 8981477
    Abstract: A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Nam Chil Moon
  • Patent number: 8975696
    Abstract: A semiconductor component may include a semiconductor layer which has a front side and a back side, a first terminal electrode on the front side, a second terminal electrode on the back side, a first dopant region of a first conduction type on the front side, which is electrically connected to one of the terminal electrodes, a second dopant region of a second conduction type in the semiconductor layer, which is electrically connected to the other terminal electrode, a pn junction being formed between the first and second dopant regions, a dielectric layer on the back side between the semiconductor layer and the second terminal electrode, and the dielectric layer having an opening through which an electrical connection between the second terminal electrode and the first or second dopant region is passed.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Oliver Haeberlen, Franz Hirler, Maximilian Roesch
  • Patent number: 8975707
    Abstract: A region for substrate potential is formed of an n-type well at a position in the direction of a channel length relative to the gate electrode and the position is between drain regions in the direction of a channel width. An n-type of a contact region with a higher concentration of n-type impurity than that of the region is provided in the region. The contact region is arranged away from the drain regions with a distance to obtain a desired breakdown voltage of PN-junction between the region and the drain region.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Ricoh Company, Ltd.
    Inventor: Masaya Ohtsuka
  • Patent number: 8969958
    Abstract: A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate positioned over a channel region and a first portion of a transition region and a polysilicon field plate positioned over a second portion of the transition region and a shallow trench isolation region. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more body extension regions, each having the same doping type as the body substrate, extend at least underneath the edge of the field plate adjacent to the gap. The body extension regions force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 3, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Vishnu Khemka, Ronghua Zhu, Tahir Arif Khan, Bernhard Heinrich Grote
  • Patent number: 8963238
    Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Wing Chor Chan, Chih-Min Hu, Shyi-Yuan Wu, Jeng Gong
  • Patent number: 8963241
    Abstract: A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate and a polysilicon field plate. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more polysilicon extension tabs extend from the field plate to at least above the edge of the first doped region. The polysilicon gate is cut to form a cut-out region for the end of each polysilicon extension tab extending toward the body substrate. The one or more polysilicon extension tabs force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Vishnu Khemka, Ronghua Zhu, Tahir Arif Khan, Bernhard Heinrich Grote
  • Patent number: 8963243
    Abstract: The p-channel LDMOS transistor comprises a semiconductor substrate (1), an n well (2) of n-type conductivity in the substrate, and a p well (3) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region (4) of p-type conductivity is arranged in the p well, and a source region (9) of p-type conductivity is arranged in the n well. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) is arranged on the gate dielectric. A body contact region (14) of n-type conductivity is arranged in the n well. A p implant region (17) is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: February 24, 2015
    Assignee: AMS AG
    Inventors: Jong Mun Park, Martin Knaipp
  • Patent number: 8957475
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the same are provided. The LDMOS device can include a drain region of a bootstrap field effect transistor (FET), a source region of the bootstrap FET, a drift region formed between the drain region and the source region, and a gate formed at one side of the source region and on the drift region.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Nam Chil Moon
  • Patent number: 8946851
    Abstract: A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate having a first doped region and a second doped region of an opposite type as the first doped region, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region and a transition region of the substrate, and a second portion forming a polysilicon field plate formed entirely over a field oxide filled trench formed in the second doped region. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap and adjacent to the trench, thereby forming a fill region having the same doping type as the first doped region.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 3, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Joel Montgomery McGregor, Vishnu Khemka
  • Patent number: 8941175
    Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: January 27, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Lin Chen, Ke-Feng Lin, Chiu-Ling Lee, Chiu-Te Lee, Chih-Chung Wang, Hsuan-Po Liao
  • Patent number: 8921927
    Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Eguchi, Yuya Abiko, Junichi Kogure
  • Patent number: 8921938
    Abstract: Some of the embodiments of the present disclosure provide a transistor comprising a p-type well; and an n-type well; wherein at least a part of one of the p-type well and the n-type well overlaps with at least a part of another of the p-type well and the n-type well. Other embodiments are also described and claimed.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: December 30, 2014
    Assignee: Marvell International Ltd.
    Inventors: Xin Yi Zhang, Weidan Li, Chuan-Cheng Cheng, Jian-Hung Lee, Chung Chyung (Jason) Han
  • Patent number: 8916931
    Abstract: An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yasuhiro Takeda, Seiji Otake
  • Patent number: 8912600
    Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: December 16, 2014
    Assignees: Silergy Technology, Silergy Semiconductor Technology (Hang-Zhou) Ltd
    Inventor: Budong You
  • Patent number: 8901649
    Abstract: A semiconductor device, an electrostatic discharge protection device and manufacturing method thereof are provided. The electrostatic discharge protection device includes a gate, a gate dielectric layer, an N-type source region, an N-type drain region, an N-type doped region and a P-type doped region. The gate dielectric layer is disposed on a substrate. The gate is disposed on the gate dielectric layer. The N-type source region and the N-type drain region are disposed in the substrate at two sides of the gate, respectively. The N-type doped region is disposed in the N-type drain region and connects to the top of the N-type drain region. The P-type doped region is disposed under the N-type drain region and connects to the bottom of the N-type drain region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: December 2, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chieh-Wei He, Shih-Yu Wang, Qi-An Xu
  • Patent number: 8884380
    Abstract: A semiconductor device which provides compactness and enhanced drain withstand voltage. The semiconductor device includes: a gate electrode; a source electrode spaced from the gate electrode; a drain electrode located opposite to the source electrode with respect to the gate electrode in a plan view and spaced from the gate electrode; at least one field plate electrode located between the gate and drain electrodes in a plan view, provided over the semiconductor substrate through an insulating film and spaced from the gate electrode, source electrode and drain electrode; and at least one field plate contact provided in the insulating film, coupling the field plate electrode to the semiconductor substrate. The field plate electrode extends from the field plate contact at least either toward the source electrode or toward the drain electrode in a plan view.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Masayasu Tanaka
  • Patent number: 8878297
    Abstract: A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well which encompasses the device region and a second device well disposed within the first device well. The device further includes a drift well which encompasses the second diffusion region of which edges of the drift well do not extend below the gate and is away from a channel region, and a drain well which is disposed under the second diffusion region and extends below the gate.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: November 4, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Ming Li
  • Patent number: 8878284
    Abstract: A protection circuit for a DMOS transistor comprises an anode circuit having a first heavily doped region of a first conductivity type (314) formed within and electrically connected to a first lightly doped region of the second conductivity type (310, 312). A cathode circuit having a plurality of third heavily doped regions of the first conductivity type (700) within a second heavily doped region of the second conductivity type (304). A first lead (202) is connected to each third heavily doped region (704) and connected to the second heavily doped region by at least three spaced apart connections (702) between every two third heavily doped regions. An SCR (400, 402) is connected between the anode circuit and the cathode circuit. The DMOS transistor has a drain (310, 312, 316) connected to the anode circuit and a source (304) connected to the cathode circuit.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Suhail Murtaza, Juergen Wittmann
  • Patent number: 8878295
    Abstract: A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: November 4, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Alexei Sadovnikov, William French, Erika Mazotti, Richard Wendell Foote, Jr., Punit Bhola, Vladislav Vashchenko
  • Patent number: 8878294
    Abstract: An inventive semiconductor device includes a semiconductor layer, a source region provided in a surface layer portion of the semiconductor layer, a drain region provided in the surface of the semiconductor layer in spaced relation from the source region, a gate insulation film provided in opposed relation to a portion of the surface of the semiconductor layer present between the source region and the drain region, a gate electrode provided on the gate insulation film, and a drain-gate isolation portion provided between the drain region and the gate insulation film for isolating the drain region and the gate insulation film from each other in non-contact relation.
    Type: Grant
    Filed: July 13, 2013
    Date of Patent: November 4, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Mitsuo Kojima, Shoji Takei
  • Patent number: 8866222
    Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Stefan Gamerith, Franz Hirler
  • Patent number: 8853780
    Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Daniel J. Blomberg, Xu Cheng, Xin Lin, Won Gi Min, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 8853022
    Abstract: A method of forming a device is presented. The method includes providing a substrate having a device region which includes a source region, a gate and a drain region defined thereon. The method also includes implanting the gate. The gate comprises one or more doped portions with different dopant concentrations. A source and a drain are formed in the source region and drain region. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Guowei Zhang
  • Patent number: 8853783
    Abstract: A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Ming Li, Jeoung Mo Koo, Purakh Raj Verma
  • Patent number: 8853784
    Abstract: A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: October 7, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Handoko Linewih, Ying-Chang Lin
  • Patent number: 8847318
    Abstract: A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Handoko Linewih, Ying-Chang Lin
  • Patent number: 8836026
    Abstract: On a doped well (2) for a drift section, at least two additional dielectric regions (7,9) having different thicknesses are present between a first contact region (4) for a drain and a second contact region (5) for source on the upper face (10) of the substrate (1), and the gate electrode (11) or an electric conductor, which is electrically conductively connected to the gate electrode, covers each of said additional dielectric regions at least partially.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: September 16, 2014
    Assignee: AMS AG
    Inventor: Georg Roehrer
  • Patent number: 8823051
    Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 2, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Micheal Harley-Stead, Jim G. Holt
  • Patent number: 8823096
    Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Su, Hsueh-Liang Chou, Ruey-Hsin Liu, Chun-Wai Ng
  • Patent number: 8823095
    Abstract: It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: September 2, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Ralf Lerner
  • Patent number: 8809950
    Abstract: A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: August 19, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Hung-Shern Tsai
  • Patent number: 8803235
    Abstract: A lateral-diffused metal oxide semiconductor device (LDMOS) includes a substrate, a first deep well, at least a field oxide layer, a gate, a second deep well, a first dopant region, a drain and a common source. The substrate has the first deep well which is of a first conductive type. The gate is disposed on the substrate and covers a portion of the field oxide layer. The second deep well having a second conductive type is disposed in the substrate and next to the first deep well. The first dopant region having a second conductive type is disposed in the second deep well. The doping concentration of the first dopant region is higher than the doping concentration of the second deep well.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corp.
    Inventors: An-Hung Lin, Hong-Ze Lin, Bo-Jui Huang, Wei-Shan Liao, Ting-Zhou Yan, Kun-Yi Chou, Chun-Wei Chen
  • Patent number: 8803236
    Abstract: An LDMOS device includes: a semiconductor layer formed over a semiconductor substrate; a gate structure disposed over the semiconductor layer; a first doped region disposed in the semiconductor layer adjacent to a first side of the gate structure; a second doped region disposed in the semiconductor layer adjacent to a second side of the gate structure; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a trench formed in the third doped region, the first doped region and the semiconductor layer under in the first doped region; an insulating layer covering the third doped region, the gate structure, and the fourth doped region; a conductive layer conformably formed over a bottom surface and sidewalls of the trench; a dielectric layer disposed in the trench; and a diffused region disposed in the semiconductor layer under the trench.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: August 12, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang
  • Patent number: 8766357
    Abstract: A high voltage MOS transistor comprises a first drain/source region formed over a substrate, a second drain/source region formed over the substrate and a first metal layer formed over the substrate. The first metal layer comprises a first conductor coupled to the first drain/source region through a first metal plug, a second conductor coupled to the second drain/source region through a second metal plug and a plurality of floating metal rings formed between the first conductor and the second conductor. The floating metal rings help to improve the breakdown voltage of the high voltage MOS transistor.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Tseng, Kun-Ming Huang, Cheng-Chi Chuang, Fu-Hsiung Yang
  • Patent number: 8759912
    Abstract: A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: June 24, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Donald R. Disney, Ognjen Milic, Kun Yi
  • Patent number: 8754497
    Abstract: An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <100> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Seetharaman Sridhar, Sameer Pendharkar, Umamaheswari Aghoram