CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation application of application Ser. No. 13/529,334, filed Jun. 21, 2012.
BACKGROUND The present invention relates to integrated circuits, and more particularly, to hybrid nanowire field effect transistor (FET) and FinFET devices and methods for fabrication thereof.
Complementary metal-oxide semiconductor (CMOS) circuits typically include a combination of n-type and p-type field effect transistor (FET) devices. Each FET device includes a source, a drain and a channel between the source and the drain. A gate electrode over and/or surrounding the channel regulates electron flow between the source and the drain.
As feature sizes of CMOS circuits get increasingly smaller (commensurate with current technology) a number of challenges arise. For instance, scaling brings about issues related to electrostatics and mobility degradation in CMOS devices. A finFET architecture offers increased scaling opportunities beyond that attainable with planar devices. FinFET devices exhibit fast switching times and high current densities.
SUMMARY According to one embodiment of the present invention, a complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer, a nanowire field effect transistor (FET) arranged on the BOX layer, the nanowire FET comprising nanowires and pads attached to the opposing ends of the nanowires, wherein the nanowires are suspended over the BOX layer by the pads arranged on the BOX layer, and a first gate stack that surrounds at least a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the first gate stack define a channel region of the nanowire FET, and a finFET arranged on the BOX layer, the FinFET comprising a plurality of fins, and a second gate stack covering at least a portion of each of the fins, wherein the portion of the fins covered by the second gate stack defines a channel region of the FinFET.
According to another embodiment of the present invention, a complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer having a first region with a first thickness and a second region with a second thickness, the first thickness is less than the second thickness, a nanowire field effect transistor (FET) arranged on the BOX layer in the first region, the nanowire FET, and a finFET arranged on the BOX layer in the second region.
A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS FIG. 1 is a three-dimensional diagram illustrating a structure for a complementary metal-oxide semiconductor (CMOS) circuit fabrication process;
FIG. 2 is a three-dimensional diagram illustrating a hardmask having been formed over a portion of the wafer;
FIG. 3 is a three-dimensional diagram illustrating a thinned region of the active layer;
FIG. 4 is a three-dimensional diagram illustrating an organic planarizing layer;
FIG. 5 is a three-dimensional diagram illustrating a fin lithography hardmask;
FIG. 6 is a three-dimensional diagram illustrating an etch;
FIG. 7 is a three-dimensional diagram illustrating the nanowires suspended over the BOX;
FIG. 8 is a three-dimensional diagram illustrating a resist layer;
FIG. 9 is a three-dimensional diagram illustrating etching the fins;
FIG. 10 is a three-dimensional diagram illustrating the removal of the resist layer;
FIG. 11 is a three-dimensional diagram illustrating the nanowires and fins having optionally been thinned and smoothed;
FIG. 12 is a three-dimensional diagram illustrating a gate stack;
FIG. 13A is a cross-sectional diagram along the line 13A of FIG. 12;
FIG. 13B is a cross-sectional diagram along the line 13B of FIG. 12;
FIG. 14 is a three-dimensional diagram illustrating spacers;
FIG. 15 is a three-dimensional diagram illustrating selective epitaxial silicon growth; and
FIG. 16 is a three-dimensional diagram illustrating a silicide formation.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1-16 illustrate an exemplary methodology for fabricating a complementary metal-oxide semiconductor (CMOS) circuit. The CMOS circuit includes an n-type field-effect transistor (NFET) device and a p-type FET (PFET) device. In the example now provided, the NFET device includes a nanowire FET architecture and the PFET includes a finFET architecture.
Referring to FIG. 1, the fabrication process begins with a semiconductor-on-insulator (SOI) wafer 100. The SOI wafer 100 includes a layer of a semiconductor material (also commonly referred to as a semiconductor-on-insulator layer or SOI layer) separated from a substrate by an insulator. When the insulator is an oxide (e.g., silicon dioxide (SiO2)), it is commonly referred to as a buried oxide, or BOX. According to the present techniques, the SOI layer will serve as an active layer of the device in which the nanowires and fins will be patterned. Thus, the SOI layer will be referred to herein as an active layer.
In the example shown in FIG. 1, the wafer 100 includes an active layer 104 disposed on a BOX 102. The BOX 102 is disposed on a substrate 101. According to an exemplary embodiment, the active layer 104 is formed from a semiconducting material, such as silicon (Si) (e.g., crystalline silicon), silicon germanium (SiGe) or germanium (Ge). Thus, the active layer 104 may also be referred to as a “semiconductor device layer” or simply as a “semiconductor layer.”
Further, as will be apparent from the following description, a thickness t of active layer 104 will be equivalent to a final desired fin height for the PFET device. According to an exemplary embodiment, active layer 104 preferably has a thickness of from about 5 nanometers (nm) to about 40 nm. Commercially available SOI wafers typically have a thicker SOI layer. Thus, the SOI layer of a commercial wafer may be thinned using techniques such as oxidative thinning to achieve the desired active layer thickness for the present techniques.
Referring to FIG. 2, a hardmask 202 is formed over a portion of the active layer 104 in which the PFET device will be formed. The hardmask 202 protects the region it covers during the active layer thinning step (described below). According to an exemplary embodiment, hardmask 202 is formed from a nitride hardmask material, such as silicon nitride (SiN) which is blanket deposited onto the active layer 104 using, e.g., low-pressure chemical vapor deposition (LPCVD), and then patterned using lithography and nitride-selective reactive ion etching (RIE) techniques known in the art to open up holes in (i.e., remove) the nitride hardmask in regions where the nanowire NFET device will be formed.
Referring to FIG. 3, a region 301 of the active layer 104 not masked by the hardmask 202 (i.e., the region that will be used to form the nanowire NFET device) is then thinned. According to an exemplary embodiment, the thinning is achieved using a timed RIE, which is selective for the material of the active layer 104 vis-à-vis the hardmask 202. Although, as shown in FIG. 3, the hardmask 202 may be thinned in the process in some embodiments. In the illustrated example, the active layer 104 is reduced in this process to a thickness t2 of from about 3 nm to about 20 nm. The result is vertical steps having been formed in the active layer 104 having a first thicker region 303 (i.e., having thickness t1) and a second thinner region 301 (i.e., having a thickness t2) having been formed in active layer 104. As described below, nanowires will be formed in this thinned region of the active layer 104.
Referring to FIG. 4, an organic planarizing layer 402 is spin-coated onto the stepped active layer 104. The organic planarizing layer 402 fills the stepped surface of the active layer 104, providing a flat planar surface for nanowire and fin patterning (described below). In the illustrated exemplary embodiment, the organic planarizing layer 402 is formed from an aromatic cross-linkable polymer (e.g., naphthalene-based) in a solvent and is coated onto the active layer 104 to a thickness of from about 30 nm to about 300 nm. Spin-coating allows the organic planarizing layer 402 to sufficiently fill the stepped topography of the active layer 104.
A post-apply bake is performed to cross-link the organic planarizing layer and bake off solvents. The post-apply bake may be, for example, conducted at a temperature of up to about 250 degrees Celsius (° C.), e.g., from about 200° C. to about 250° C.
Standard lithography techniques are used to pattern a first hardmask 502, which will be used to pattern fins in the thicker region 303 of the active layer 104 (also referred to herein as a fin lithography hardmask) and a second hardmask 504, which will be used to pattern nanowires (and pads) in the thinner region 301 of the active layer 104 (also referred to herein as a nanowire/pad lithography hardmask). Since the organic planarizing layer 402 provides a continuous flat surface over the two regions of the active layer, the hardmasks 502 and 504 may be formed from a common material, using a single hardmask fabrication process. For example, a suitable hardmask material (e.g., a nitride material, such as SiN) may be blanket deposited over the organic planarizing layer 402 and patterned using a standard photolithography process with the footprint and location of hardmasks 502 and 504. As shown in FIG. 5, the fin lithography hardmask 502 is patterned on the organic planarizing layer 402 over the thicker region 303 of the active layer 104 and the nanowire/pad lithography hardmask 504 is patterned on the organic planarizing layer 402 over the thinner region 301 of the active layer 104.
The fin lithography hardmask 502 will dictate the dimensions and spacing (i.e., pitch, or distance between fins) in the final FinFET device. Thus, the fin lithography hardmask 502 is patterned with the desired dimensions and pitch commensurate with those of the fins. As shown in FIG. 5, the nanowire/pad hardmask 504 has a ladder-like configuration. This ladder-like configuration will be transferred to the active layer 104, wherein the nanowires will be patterned like rungs of a ladder interconnecting the pads (described below). The pads will be used to form source and drain regions of the nanowire FET. For some advanced patterning techniques such as sidewall image transfer, it may be preferable for the nanowires and fins to have the same lithographic width w.
Referring to FIG. 6, an etch through the hardmasks 502, 504, and the organic planarizing layer 402 is performed to form nanowires and pads in the thinner region 301 of the active layer 104 and only partially etch the fins in the thicker region of the active layer 104. For example, the etch may be performed using a series of RIE processes. For example, a first RIE process may be used that is selective for etching the organic planarizing layer 402. This first RIE process can be performed using, for example, an oxygen-containing, e.g., N2/O2 chemistry. A second RIE process may then be used to transfer the fin pattern into the hardmask 202, forming a patterned hardmask 601. The second RIE process may be performed using, for example, a CF4 etch chemistry. A third RIE process may be used to transfer the nanowire/fin pattern into the active layer 104. The third RIE step may be performed using, for example, a fluorine-containing, e.g., CHF3/CF4, or bromine chemistry. The third RIE is end-pointed when the nanowires 602 and pads 604 in the thinner region 301 of the active layer 104 are fully etched, and any remaining organic planarizing layer 402 is stripped with, for example, a wet strip or O2 plasma. At this point the fins 606 in the thicker region 303 of the active layer 104 are partially etched. Namely, this third etch process into the active layer 104 only extends part way through the thicker region 303 of the active layer 104. The remaining active layer protects the BOX 102 in the thicker region 303 during the process of undercutting the BOX 102 in the thinner region 301 below the nanowires 602 (described below).
As shown in FIG. 6, the nanowires 602 and pads 604 are formed having a ladder-like configuration. Namely, the pads are attached at opposite ends of the nanowires similar to the rungs of a ladder.
In FIG. 7, the nanowires are suspended over the BOX 102. In the illustrated exemplary embodiment, the nanowires 602 are suspended by undercutting the BOX 102 beneath the nanowires 602 using an isotropic etching process. This process laterally etches portions of the BOX 102 under the pads 604 resulting in undercut regions 702 defined by the removal of portion of the BOX 102. The isotropic etching of the BOX 102 may be performed, for example, using a diluted hydrofluoric acid (DHF). A 100:1 DHF etches approximately 2 nm to 3 nm of BOX layer 102 per minute at room temperature. As highlighted above, the incomplete etch in the thicker active regions 303 where the fins are formed protects the fins from BOX undercut during this step.
Following the isotropic etching of the BOX 102 the nanowires 602 may be smoothed to give them an elliptical and in some cases a cylindrical cross-sectional shape. The smoothing of the nanowires 602 may be performed, for example, by annealing the nanowires 602 in a hydrogen-containing atmosphere. Exemplary annealing temperatures may be from about 600° C. to about 1,000° C., and a hydrogen pressure of from about 600 torr to about 700 torr may be employed.
Referring to FIG. 8, a resist layer 802 is formed over the nanowires 602 and pads 604 (of FIG. 7), to protect the nanowires 602 and pads 604 during etching of the fins. The resist 802 may be formed by coating a suitable resist material and patterning using lithography and etching processes. Exemplary resist materials include, for example, poly(methyl methacrylate) (PMMA).
FIG. 9 illustrates the resultant structure following an etching process that removes exposed portions of the active layer 104 (of FIG. 8) and completes the patterning of the fins 606. The etching process may include any suitable etching process such as, for example, a RIE process. The patterned hardmask 601 on the fins 606 is thinned during this fin etching process. The remaining patterned hardmask 601 may optionally be removed using for example an RIE process. Alternatively, as shown in the figures, the remaining patterned hardmask 601 may be removed later in the process.
Following the fin etch, the resist 802 (of FIG. 9) may be removed using, for example, a resist stripper. Suitable resist strippers include, for example, N-methyl pyrolidinone (NMP).
Optionally, the nanowires 602 and fins 606 may be additionally thinned and smoothed as shown in FIG. 11. In this regard, in a similar manner as described above, the nanowires 602 may be re-shaped (e.g., smoothed) to an elliptical (e.g., circular) cross-sectional shape earlier in the process. The nanowires and fins may be thinned using a high-temperature (e.g., from about 700° C. to about—1,000° C.) oxidation of the nanowires 602 and fins 606 followed by etching of the grown oxide (not shown). The oxidation and etching process may be repeated x number of times to achieve desired nanowire 602 and fin 606 dimensions.
FIG. 12 illustrates the resultant structure after a gate stack 1202 is patterned on the nanowires 602 and a gate stack 1204 is patterned on the fins 606. The portions of the nanowires 602 and fins 606 surrounded/covered by the gates stacks 1202 and 1204 respectively will serve as channel regions of the respective FET devices. The gate stack 1202 includes a dielectric (or combination of dielectrics), a first gate material (such as a metal(s)) and optionally a second gate material 1208 (such as a metal or doped polysilicon layer), all that surround the nanowires. Gate stack 1204 contains a dielectric (or combination of dielectrics), a first gate material (such as a metal(s)) and optionally a second gate material 1208 (such as a metal or doped polysilicon layer) that covers at least a portion of the fins, wherein the gate dielectric separates the gate materials 1208 from the fins. For example, as will be apparent from the following description, the second gate material 1208 in gate stack 1202 and the second gate material 1208 in gate stack 1204 are preferably formed from the same material that is deposited over both of the gate stacks and then patterned.
As shown in FIG. 12, since the nanowires have been suspended over the BOX as described above, gate stack 1202 completely surrounds at least a portion of each of the nanowires. This is referred to as a gate-all-around (GAA) configuration.
According to an exemplary embodiment, gate stacks 1202 and 1204 are formed by depositing a conformal gate dielectric film 1302 such silicon dioxide (SiO2), silicon oxynitride (SiON), or hafnium oxide (HfO2) (or other hi K material) around both the nanowires (labeled “NW”) and the fins, respectively. See FIG. 13A which provides a view of a cross-sectional cut (along line 13A of FIG. 12) through a portion of gate stack 1202 and FIG. 13B which provides a view of a cross-sectional cut (along line 13B, of FIG. 12) through a portion of gate stack 1204. Optionally, a second conformal gate dielectric film 1304 that includes, for example, HfO2, may be applied over gate dielectric film 1302. A (first) gate material 1306 is deposited over the conformal gate dielectric film 1302 (or over optional second conformal gate dielectric film 1304). According to an exemplary embodiment, the gate material 1306 is a conformal metal gate film that includes, for example, tantalum nitride (TaN) or titanium nitride (TiN).
Optionally, a second gate material such as doped polysilicon or metal may be blanket deposited onto the structure (i.e., over the gate material 1306 so as to surround portions of the nanowires 602 and fins 606. Referring to FIG. 12, hardmasks 1210 (e.g., a nitride hardmask, such as SiN) may then be formed on the second gate material 1208, wherein the hardmasks 1210 correspond to gate lines of the nanowire FET and FinFET. Standard patterning techniques can be used to form the hardmasks 1210. The gate material(s) and dielectric(s) are then etched by directional etching that results in straight sidewalls of the gate stacks 1202 and 1204, as shown in FIG. 12. The second gate material 1204, by this etching process, forms second gate material 1208 over gate stacks 1202 and 1204, respectively. If present, any remaining hardmask 601 on the fins 606 is also removed by the etching (illustrated in FIG. 14).
Referring to FIG. 14, spacers 1402 are formed on opposing sides of gate stack 1202 and spacers 1404 are formed on opposing sides of gate stack 1204. In the illustrated exemplary embodiment, spacers 1402 and 1404 are formed by, for example, depositing a blanket dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by RIE. As shown in FIG. 14, some of the deposited spacer material may remain in the undercut regions 702, since the RIE in that region is blocked by the pads.
FIG. 15 illustrates the resultant structure following the growth of a selective epitaxial material such as silicon (Si), silicon germanium (SiGe), or silicon carbide (SiC) 1502 to thicken the exposed portions of the nanowires 602, pads 604 and fins 606 (i.e., those portions not covered by a gate stack or spacers). As shown in FIG. 15, the epitaxial silicon may merge the fins together with epitaxial silicon. The growth process might involve epitaxially growing, for example, in-situ doped Si or SiGe that may be either n-type or p-type doped. The in-situ doped epitaxial growth process forms source (S) and drain (D) regions of the nanowire FET 1501 and of the FinFET 1503. For example, a chemical vapor deposition (CVD) reactor may be used to perform the epitaxial growth. For example, for silicon epitaxy, precursors include, but are not limited to, SiCl4, SiH4 combined with HCL. The use of chlorine allows selective deposition of silicon only on exposed silicon. A precursor for SiGe growth may be GeH4, which may obtain deposition selectivity without HCL. Precursors for dopants may include PH3 or AsH3 for n-type doping and B2H6 for p-type doping. Deposition temperatures may range from about 550° C. to about 1,000° C. for pure silicon deposition, and as low as 300° C. for pure Ge deposition.
FIG. 16 illustrates the resultant structure following the formation of a contact material such as a silicide, germanide, germanosilicide, etc. 1602 that is formed on the exposed epitaxial silicon 1502. Examples of contact materials include, but are not limited to, nickel silicide or cobalt silicide. When nickel (Ni) is used, the nickel silicide phase is formed due to its low resistivity. By way of example only, formation temperatures can be from about 400° C. to about 600° C. Once the contact material formation is performed, capping layers and vias for connectivity (not shown) may be formed.
Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.
