With One-dimensional Charge Carrier Gas Channel (e.g., Quantum Wire Fet) (epo) Patents (Class 257/E29.245)
  • Patent number: 9721846
    Abstract: The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: August 1, 2017
    Assignee: ZING SEMICONDUCTOR CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 9000485
    Abstract: An electrode structure, a GaN-based semiconductor device including the electrode structure, and methods of manufacturing the same, may include a GaN-based semiconductor layer and an electrode structure on the GaN-based semiconductor layer. The electrode structure may include an electrode element including a conductive material and a diffusion layer between the electrode element and the GaN-based semiconductor layer. The diffusion layer may include a material which is an n-type dopant with respect to the GaN-based semiconductor layer, and the diffusion layer may contact the GaN-based semiconductor layer. A region of the GaN-based semiconductor layer contacting the diffusion layer may be doped with the n-type dopant. The material of the diffusion layer may comprise a Group 4 element.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-yub Lee, Wenxu Xianyu, Chang-youl Moon, Yong-young Park, Woo-young Yang, In-jun Hwang
  • Patent number: 8993991
    Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device includes a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface disposed between the first and second top surfaces, a first source/drain region formed under the first top surface, a first nanowire extended from the first perpendicular surface in one direction and being spaced apart from the second top surface, a second nanowire extended from a side surface of the first nanowire in the one direction, being spaced apart from the second top surface, and including a second source/drain region, a gate electrode on the first nanowire, and a dielectric layer between the first nanowire and the gate electrode.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 31, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dongwoo Suh, Sung Bock Kim, Hojun Ryu
  • Patent number: 8987071
    Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 24, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Min-Cheng Chen, Chang-Hsien Lin, Chia-Yi Lin, Tung-Yen Lai, Chia-Hua Ho
  • Patent number: 8980736
    Abstract: A method of manufacturing a semiconductor device may include: forming active patterns of pillar-shapes upward protruding from a substrate, the active patterns fully doped with dopants of one conductivity type; forming a gate electrode extending in one direction, the gate electrode overlapped with sidewalls of the active patterns; and forming a gate insulating layer between the gate electrode and the active patterns.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong Un Kim
  • Patent number: 8946789
    Abstract: An example embodiment relates to a transistor including a channel layer. A channel layer of the transistor may include a plurality of unit layers spaced apart from each other in a vertical direction. Each of the unit layers may include a plurality of unit channels spaced apart from each other in a horizontal direction. The unit channels in each unit layer may form a stripe pattern. Each of the unit channels may include a plurality of nanostructures. Each nanostructure may have a nanotube or nanowire structure, for example a carbon nanotube (CNT).
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-kook Kim, Woong Choi, Sang-yoon Lee
  • Patent number: 8907377
    Abstract: A higher electron mobility transistor (HEMT) and a method of manufacturing the same are disclosed. According to example embodiments, the HEMT may include a channel supply layer on a channel layer, a source electrode and a drain electrode that are on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a source pad and a drain pad. The source pad and a drain pad electrically contact the source electrode and the drain electrode, respectively. At least a portion of at least one of the source pad and the drain pad extends into a corresponding one of the source electrode and drain electrode that the at least one of the source pad and the drain pad is in electrical contact therewith.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-chul Jeon, Ki-yeol Park, Young-hwan Park, Jai-kwang Shin, Jae-joon Oh, Hyuk-soon Choi, Jong-bong Ha
  • Patent number: 8889564
    Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, James J. Demarest, Balasubramanian S. Haran
  • Patent number: 8884266
    Abstract: A thin film transistor includes a gate electrode configured to receive a control voltage, a source electrode insulated from the gate electrode, and configured to receive an input voltage, a drain electrode insulated from the gate electrode, and configured to receive an output voltage, at least two carbon nanotube patterns formed in a channel region between the source electrode and the drain electrode, wherein the carbon nanotube patterns are separated from each other, and at least one floating electrode connecting the two carbon nanotube patterns to each other.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: November 11, 2014
    Assignees: Samsung Display Co., Ltd., SNU R&DB Foundation
    Inventors: Sang Ho Park, Young Ki Shin, Yoon Ho Khang, Joo Hyung Lee, Hyung Woo Lee, Seung Hun Hong
  • Patent number: 8860134
    Abstract: A trench power device includes a semiconductor layer, a trench gate structure, a trench source structure, and a contact. The semiconductor layer has an epitaxial layer, a doped body region, a S/D region, and a doped contact-carrying region. The doped body region is formed in the epitaxial layer, the S/D region is formed in the doped body region, and the doped contact-carrying region is formed in the doped body region and outside a projecting portion defined by orthogonally projecting from the S/D region to the doped body region. The trench gate structure is embedded in the S/D region, the doped body region, and the epitaxial layer. The trench source structure is embedded in the doped body region and the epitaxial layer, and is connected to the doped contact-carrying region. The contact is connected to the S/D region and the doped contact-carrying region.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: October 14, 2014
    Assignee: Sinopower Semiconductor, Inc.
    Inventor: Po-Hsien Li
  • Patent number: 8829625
    Abstract: In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey W. Sleight, Sarunya Bangsaruntip, Sebastian U. Engelmann, Ying Zhang
  • Patent number: 8823077
    Abstract: A semiconductor device according to example embodiments may include a channel including a nanowire and a charge storage layer including nanoparticles. A twin gate structure including a first gate and a second gate may be formed on the charge storage layer. The semiconductor device may be a memory device or a diode.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: September 2, 2014
    Assignees: Samsung Electronics Co., Ltd., SNU R&D Foundation
    Inventors: Eun-Hong Lee, Seung-Hun Hong, Un-jeong Kim, Hyung-Woo Lee, Sung Myung
  • Patent number: 8816328
    Abstract: A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B Chang, Martin Glodde, Michael A. Guillorn
  • Patent number: 8803129
    Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B Chang, Martin Glodde, Michael A. Guillorn
  • Patent number: 8785912
    Abstract: Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 22, 2014
    Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation
    Inventors: Hyun-jong Chung, Jae-hong Lee, Jae-ho Lee, Hyung-cheol Shin, Sun-ae Seo, Sung-hoon Lee, Jin-seong Heo, Hee-jun Yang
  • Patent number: 8754393
    Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8754401
    Abstract: An Impact Ionization Field-Effect Transistor (I-MOS) device in which device degradation caused by hot carrier injection into a gate oxide is prevented. The device includes source, drain, and gate contacts, and a channel between the source and the drain. The channel has a dimension normal to the direction of a charge carrier transport in the channel such that the energy separation of the first two sub-bands equals or exceeds the effective energy band gap of the channel material.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mikael T Bjoerk, Oliver Hayden, Joachim Knoch, Emanuel Loertscher, Heike E Riel, Walter Heinrich Riess, Heinz Schmid
  • Patent number: 8748940
    Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
  • Patent number: 8716072
    Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Josephine B. Chang, Leland Chang, Jeffrey W. Sleight
  • Patent number: 8698129
    Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 15, 2014
    Assignees: IMEC, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Geert Hellings, Geert Eneman
  • Publication number: 20140091279
    Abstract: Non-planar semiconductor devices having germanium-based active regions with release etch-passivation surfaces are described. For example, a semiconductor device includes a vertical arrangement of a plurality of germanium-rich nanowires disposed above a substrate. Each nanowire includes a channel region having a sulfur-passivated outer surface. A gate stack is disposed on and completely surrounds the channel region of each of the germanium-rich nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the sulfur-passivated outer surface and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the germanium-rich nanowires.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Jessica S. Kachian, Willy Rachmady, Robert B. Turkot, Jr.
  • Patent number: 8686485
    Abstract: A semiconductor device may include active patterns of pillar-shapes disposed on a substrate and spaced apart from each other in one direction; a gate electrode extending in the one direction and overlapped with sidewalls of the active patterns; a gate insulating layer disposed between the gate electrode and the active patterns; bit lines connected to bottom surfaces of respective active patterns; and/or capacitors connected to top surfaces of the respective active patterns. Each of the active patterns may have no p-type/n-type (PN) junctions. A semiconductor device may include a substrate; active patterns on the substrate that are spaced apart from each other; a gate electrode configured to overlap sidewalls of the active patterns; and/or gate insulating layers between the gate electrode and respective active patterns. The active patterns may be doped with dopants of a same conductivity type.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong Un Kim
  • Publication number: 20140084249
    Abstract: A nanowire field effect transistor device includes a first nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, and a second nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a plane, the plane arranged substantially orthogonal to a plane defined by a planar surface of the substrate.
    Type: Application
    Filed: October 23, 2012
    Publication date: March 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20140084246
    Abstract: Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Ravi Pillarisetty, Niti Goel, Han Wui Then, Van H. Le, Willy Rachmady, Marko Radosavljevic, Gilbert Dewey, Benjamin Chu-Kung
  • Publication number: 20140054549
    Abstract: A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 27, 2014
    Applicant: SEMATECH, INC.
    Inventors: Wei-Yip LOH, Wei-E WANG
  • Publication number: 20140042392
    Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.
    Type: Application
    Filed: August 14, 2012
    Publication date: February 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Qing Cao, Aaron D. Franklin, Joshua T. Smith
  • Patent number: 8648324
    Abstract: Glassy carbon nanostructures are disclosed that can be used as electrode materials in batteries and electrochemical capacitors, or as photoelectrodes in photocatalysis and photoelectrochemistry devices. In some embodiments channels (e.g., substantially cylindrically-shaped pores) are formed in a glassy carbon substrate, whereas in other embodiments, ridges are formed that extend along and over a glassy carbon substrate. In either case, a semiconductor and/or metal oxide may be deposited over the glassy carbon to form a composite material.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ho-Cheol Kim, Sang-Min Park
  • Publication number: 20140034905
    Abstract: Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX. Nanowire cores and pads are etched in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial shells are formed surrounding each of the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores/epitaxial shells, wherein the portions of the nanowire cores/epitaxial shells surrounded by the gate stack serve as channels of the device, and wherein the pads and portions of the nanowire cores/epitaxial shells that extend out from the gate stack serve as source and drain regions of the device.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy Cohen, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8642997
    Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Alberto Valdes Garcia
  • Patent number: 8637849
    Abstract: A Vertical Field Effect Transistor (VFET) formed on a substrate, with a conductive bottom electrode formed thereon. A bottom dielectric spacer layer and a gate dielectric layer surrounded by a gate electrode are formed thereabove. Thereabove is an upper spacer layer. A pore extends therethrough between the electrodes. A columnar Vertical Semiconductor Nanowire (VSN) fills the pore and between the top and bottom electrodes. An FET channel is formed in a central region of the VSN between doped source and drain regions at opposite ends of the VSN. The gate dielectric structure, that is formed on an exterior surface of the VSN above the bottom dielectric spacer layer, separates the VSN from the gate electrode.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw
  • Publication number: 20140014904
    Abstract: In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 16, 2014
    Applicant: International Business Machines Corporation
    Inventors: Guy M. Cohen, Michael A. Guillorn
  • Patent number: 8624318
    Abstract: A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Zhong-Xiang He, Qizhi Liu
  • Publication number: 20130341596
    Abstract: A complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer having a first region with a first thickness and a second region with a second thickness, the first thickness is less than the second thickness, a nanowire field effect transistor (FET) arranged on the BOX layer in the first region, the nanowire FET, and a finFET arranged on the BOX layer in the second region.
    Type: Application
    Filed: July 13, 2012
    Publication date: December 26, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8604462
    Abstract: A photodetector includes: a substrate; a first dielectric material positioned on the substrate; an optical waveguide positioned on the first dielectric material; a second dielectric material positioned on the optical waveguide; a graphene layer positioned on the second dielectric material; and a first electrode and a second electrode that are positioned on the graphene layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 10, 2013
    Assignee: Electronics & Telecommunications Research Institute
    Inventor: Jin Tae Kim
  • Patent number: 8586966
    Abstract: A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Shreesh Narasimha, Jeffrey W. Sleight
  • Patent number: 8575653
    Abstract: Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: November 5, 2013
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Robert Chau
  • Patent number: 8564031
    Abstract: The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 22, 2013
    Assignee: Peking University
    Inventors: Ru Huang, Jibin Zou, Runsheng Wang, Gengyu Yang, Yujie Ai, Jiewen Fan
  • Publication number: 20130270521
    Abstract: A technique for a nanodevice is provided. A reservoir is separated into two parts by a membrane. A nanopore is formed through the membrane, and the nanopore connects the two parts of the reservoir. The nanopore and the two parts of the reservoir are filled with ionic buffer. The membrane includes a graphene layer and insulating layers. The graphene layer is wired to first and second metal pads to form a graphene transistor in which transistor current flowing through the graphene transistor is modulated by charges passing through the nanopore.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hongbo Peng, Gustavo A. Stolovitzky, Wenjuan Zhu
  • Patent number: 8558218
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: October 15, 2013
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh, Chris Matayabas
  • Publication number: 20130248823
    Abstract: A semiconductor device includes a substrate, first plural contacts formed in the substrate, a graphene layer formed on the substrate and on the first plural contacts and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: International Business Machines Corporation
    Inventors: Ageeth Anke Bol, Aaron Daniel Franklin, Shu-Jen Han
  • Publication number: 20130234762
    Abstract: A circuit includes a negative differential resistance (NDR) device which includes a gate and a graphene channel, and a gate voltage source which modulates a gate voltage on the gate such that an electric current through the graphene channel exhibits negative differential resistance.
    Type: Application
    Filed: March 12, 2012
    Publication date: September 12, 2013
    Applicant: International Business Machines Corporation
    Inventors: Shu-Jen Han, Yu-Ming Lin, Yanqing Wu
  • Publication number: 20130221319
    Abstract: Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 29, 2013
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey W. Sleight, Josephine B. Chang, Isaac Lauer, Shreesh Narasimha
  • Publication number: 20130221328
    Abstract: A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 29, 2013
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey W. Sleight, Josephine B. Chang, Isaac Lauer, Shreesh Narasimha
  • Patent number: 8519479
    Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight
  • Publication number: 20130207079
    Abstract: Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey W. Sleight, Sarunya Bangsaruntip
  • Publication number: 20130207080
    Abstract: A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christos D. Dimitrakopoulos, Damon B. Farmer, Alfred Grill, Yu-Ming Lin, Deborah A. Neumayer, Dirk Pfeiffer, Wenjuan Zhu
  • Publication number: 20130193410
    Abstract: Semiconductor nano-devices, such as nano-probe and nano-knife devices, which are constructed using graphene films that are suspended between open cavities of a semiconductor structure. The suspended graphene films serve as electro-mechanical membranes that can be made very thin, from one or few atoms in thickness, to greatly improve the sensitivity and reliability of semiconductor nano-probe and nano-knife devices.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 1, 2013
    Applicant: International Business Machines Corporation
    Inventor: Wenjuan Zhu
  • Publication number: 20130175504
    Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.
    Type: Application
    Filed: March 31, 2012
    Publication date: July 11, 2013
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Sagy Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam Geha
  • Publication number: 20130175505
    Abstract: A thin film transistor (“TFT”) includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode and a semiconductor layer. The gate insulating layer is disposed on the gate electrode. The source electrode is disposed on the gate insulating layer. The drain electrode is disposed on the gate insulating layer. The drain electrode is spaced apart from the source electrode. The semiconductor layer is disposed on the gate insulating layer. The semiconductor layer makes contact with a side surface of the source electrode and a side surface of the drain electrode.
    Type: Application
    Filed: August 14, 2012
    Publication date: July 11, 2013
    Inventors: Woo-Yong SUNG, Dong-Hwan KIM, Jeong-Ho LEE, Tae-Woon CHA, Sang-Gun CHOI
  • Publication number: 20130175503
    Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicant: International Business Machines Corporation
    Inventors: Guy Cohen, Michael A. Guillorn, Conal Eugene Murray