SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH A CURRENT CARRYING REGION AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF
Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a current carrying region (e.g., a source region of the first conductivity type and/or a drain region of the second conductivity type), and the resistor circuit is connected between the isolation structure and the current carrying region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).
Embodiments generally relate to semiconductor devices and their manufacturing methods, and more particularly relate to laterally diffused metal oxide semiconductor (LDMOS) devices with isolation structures.
BACKGROUNDIn some system-on-a-chip (SOC) applications that include an inductive load, certain nodes may experience a negative potential during switching, which may lead to significant injection current into the substrate. The charged carriers injected into the substrate may disturb adjacent circuits and adversely affect their operation.
Accordingly, there is an ongoing need for improved device structures, materials and methods of fabrication that can overcome this difficulty and provide improved performance. It is further desirable that the methods, materials, and structures employed be compatible with present day manufacturing capabilities and materials and not require substantial modifications to available manufacturing procedures or substantial increases in manufacturing costs. Furthermore, other desirable features and characteristics of the various embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
Embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and
The following detailed description is merely exemplary in nature and is not intended to limit the embodiments or the application and uses of the various embodiments. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field or background, or the following detailed description.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the description of the embodiments. Additionally, elements in the drawings figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in some of the figures may be exaggerated relative to other elements or regions of the same or other figures to help improve understanding of the various embodiments.
The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described herein are, for example, capable of use in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms “left,” right,” “in,” “out,” “front,” “back,” “up,” “down, “top,” “bottom,” “over,” “under,” “above,” “below” and the like in the description and the claims, if any, are used for describing relative positions and not necessarily for describing permanent positions in space. It is to be understood that the embodiments described herein may be used, for example, in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner.
The various embodiments of the invention described here are illustrated by semiconductor devices and structures of particular conductivity type having various P and N doped regions appropriate for that conductivity type device or structure. But this is merely for convenience of explanation and not intended to be limiting. Persons of skill in the art will understand that devices or structures of opposite conductivity type may be provided by interchanging conductivity types so that a P-type region becomes an N-type region and vice versa. Alternatively, the particular regions illustrated in what follows may be more generally referred to as of a “first conductivity type” and a “second” opposite conductivity type”, wherein the first conductivity type may be either N or P type and the second opposite conductivity type is then either P or N type, and so forth. Further, for convenience of explanation and not intended to be limiting, various embodiments of the present invention are described herein for silicon semiconductors, but persons of skill in the art will understand the invention is not limited to silicon but applies to a wide variety of semiconductor materials. Non-limiting examples are other type IV semiconductor materials, as well as type III-V and II-VI semiconductor materials, organic semiconductor materials and combinations thereof, whether in bulk form or in layered form or in thin film form or semiconductor-on-insulator (SOI) form or combinations thereof. Such materials may be single-crystal or poly-crystalline or amorphous or combinations thereof.
According to an embodiment, driver circuit 110 is part of a system-on-a-chip (SOC), where the driver circuit 110 and other portions of the SOC are formed on a single semiconductor substrate (referred to below as the “SOC substrate”). For example, the SOC also may include various processing components, memory arrays (e.g., flash arrays, static random access memory (SRAM) arrays, and so on), and other circuitry. For simplicity, other portions of the SOC are not illustrated in
Driver circuit 110 and other portions of the SOC are coupled with the external circuit 130 via at least “high side gate” (HG) pin 140, “high side source” (HS) pin 141, “low side gate” (LG) pin 142, a “low side source” (LS) pin 143, and ground pin 144. Although referred to as “pins” herein, pins 140-144 may include any combination of pins, leads, bumps, balls, or other types of contacts. In
As mentioned above, external circuit 130 includes an inductive load 132, a first “high side” FET 133, a second “low side” FET 134, and a shunt resistor 136, in an embodiment. As will be explained in more detail later, under certain circumstances, inductive load 132 may function as a source of injected current, which couples to the driver circuit 110. The high side FET 133 and the low side FET 134 each include a body diode, as shown in
According to an embodiment, driver circuit 110 includes, along a first current path, at least a first N-type LDMOS field effect transistor (NLDMOSFET) 112 and at least a first P-type LDMOSFET (PLDMOSFET) 116. Node 150 couples the drain of NLDMOSFET 112 and the source and body of PLDMOSFET 116 to HG pin 140. Node 151 couples the source and body of NLDMOSFET 112 and the drain of PLDMOSFET 116 to HS pin 141. Along a second current path, driver circuit 110 also may include a second NLDMOSFET 114 and a second PLDMOSFET 118. Node 152 couples the drain of NLDMOSFET 114 and the source and body of PLDMOSFET 118 to LG pin 142. Node 153 couples the source and body of NLDMOSFET 114 and the drain of PLDMOSFET 118 to LS pin 143. The SOC substrate is connected to system ground through ground pin 144.
As will be explained in more detail later in conjunction with the other figures, the active areas of PLDMOSFETs 116 and 118 each may be formed within an isolation structure or isolation “tub” (e.g., an N-type buried layer and N-type sinker region that surrounds the active area). In addition, the active areas of NLDMOSFETS 112 and 114 each similarly may be formed within an isolation structure. The isolation structures are configured to isolate the active areas of NLDMOSFETs 112 and 114 and PLDMOSFETs 116 and 118 from the remainder of the SOC substrate. The isolation structures may allow NLDMOSFETs 112 and 114 and PLDMOSFETs 116 and 118 to operate with a body bias. In addition, the isolation structures may help to prevent current injection into the SOC substrate under normal operating conditions. For example, as represented in
In some systems, the source regions of PLDMOSFETs 116 and 118 and their associated isolation structures are electrically shorted through metallization so that the source regions and the isolation structures always are at a same potential. In addition, in the PLDMOSFETs 116 and 118, the body region may be merged with the isolation structure at the substrate surface, in which case the isolation structure (or more specifically the N-type sinker region) may be considered to be a body tie. The source region and body region typically are held at high potentials (e.g., Vdd), and shorting the sources with the isolation structures while merging the isolation structure and the body region enables the portion of the substrate between the body region and the N-type buried layer to better sustain full reverse bias at maximum Vdd. Similarly, the drain regions of NLDMOSFETs 112 and 114 and their associated isolation structures may be electrically shorted through metallization so that the drain regions and the isolation structures always are at a same potential. This arrangement is beneficial because, in the NLDMOSFETs 112 and 114, the substrate material between the drift region and each isolation structure's buried layer may not be able to sustain a full reverse bias at maximum Vdd from both the drift region and the buried layer.
While shorting together the current carrying regions (e.g., drain regions of the NLDMOSFETs 112 and 114, and source regions of the PLDMOSFETs 116 and 118) to the isolation structures of NLDMOSFETs 112 and 114 and the body of PLDMOSFETs 116 and 118, respectively, may work well under many operating conditions, this arrangement may allow undesirable current to be injected into the substrate of the SOC under certain other operating conditions. For example, at the moment that the driver circuit 110 turns the high side FET 133 off (e.g., by turning on NLDMOSFET 112), the low side FET 134 also is off (e.g., NLDMOSFET 114 is conducting). In this state, the current in the inductive load 132 may push the HS pin 141 negative until the body diode of the low side FET 134 is forward biased. The driver circuit 110 may be controlled to turn on the low side FET 134 in order to lower the power dissipation of the low side FET 134 some time later. Then, the negative potential at node 120 and the HS pin 141 (and thus the source and body of NLDMOSFET 112) is defined by the inductive load current times the sum of the resistance of shunt resistor 136 and the RDSON of the low side FET 134. On the LS pin 143 (and the source and body of NLDMOSFET 114), a lesser negative potential is defined by the inductive load current times the resistance of the shunt resistor 136. For a while after the high side FET 133 is turned off, the NLDMOSFETs 112 and 114 have positive gate-source voltages (Vgs), thus causing the drains to short with the sources of NLDMOSFETs 112 and 114. In systems in which the drain electrodes and isolation structures of NLDMOSFETs 112 and 114 are merely shorted, the negative potentials on the HS pin 141 and the LS pin 143 may then access nodes 150, 152 and at least two injecting sites (N-type areas) in the SOC substrate through the conducting channels of NLDMOSFETs 112 and 114. Because the negative potential on the HS pin 141 is greater than the negative potential on the LS pin 143, the potential for current injection as a result of the negative potential on the HS pin 141 is a larger issue than the potential for current injection as a result of the negative potential on the LS pin 143. To avoid the high power dissipation in the body diode of low side FET 134 for an extended period of time, low side FET 134 is turned on (i.e., by turning off NLDMOSFET 114) shortly after the high side FET 133 is turned off. However, the potential at node 120 (and thus HS pin 141) will still be negative, and the issue of current injection may still exist, although to a lesser extent.
According to various embodiments, driver circuit 110 includes further circuitry configured to reduce current injection into the SOC substrate under the above-described or other operating conditions. More particularly, in an embodiment, driver circuit 110 includes a first resistor circuit 160 coupled between the drain region and the isolation structure of NLDMOSFET 112, a second resistor circuit 161 coupled between the drain region and the isolation structure of NLDMOSFET 114, a third resistor circuit 162 coupled between the source region and the isolation structure of PLDMOSFET 116, and a fourth resistor circuit 163 coupled between the source region and the isolation structure of PLDMOSFET 118. By inserting the resistor circuits 160-163 at these locations, the injection current can be reduced. More specifically, the injection sites are moved behind resistor circuits 160-163, thus significantly limiting the current that may be injected into the SOC substrate at a given potential on the HS pin 141 and/or the LS pin 143. Although not illustrated in
As used herein, a “resistor circuit” is a circuit that includes one or more resistors or resistive networks. When referring to “a resistive network” herein, it is to be understood that the term may include a single resistor or an arrangement of resistors in series or parallel. As will be explained in more detail later, embodiments of “resistor circuits” discussed herein include at least one resistive network, and also may include one or more other components (e.g., one or more diodes or other components in series and/or parallel with the resistive network(s) of the resistor circuit). As will be described in more detail later in conjunction with the remaining figures, a resistor forming a portion of a resistor circuit may be formed from polycrystalline silicon, although it is to be understood that a resistor may be formed from other materials, as well. A “diode” may include a single diode or multiple diodes interconnected in series and/or parallel. In various embodiments, a diode may be formed from a Schottky contact and a doped semiconductor region, a PN junction, a polycrystalline silicon diode, and combinations of these or other diode components.
Embodiments of NLDMOSFETs (e.g., NLDMOSFET 112), PLDMOSFETs (e.g., PLDMOSFET 116) and associated resistor circuits (e.g., resistor circuits 160 and 162) are described in more detail below. More specifically,
NLDMOSFET 200 is formed in and on a semiconductor substrate 210 (e.g., the SOC substrate discussed in conjunction with
NLDMOSFET 200 further includes an active device formed within the active area 230. According to an embodiment, the active device includes an N-type drift region 232, a P-type body region 234, an N-type drain region 236, an N-type source region 238, a P-type body contact region 240 (also referred to as a “body tie”), and a gate electrode 242 (and corresponding gate dielectric, not numbered). Drain region 236 and source region 238 may be referred to herein as “current carrying regions,” to differentiate these regions from the gate of NLDMOSFET 200, which is not a current carrying region. The use of the term “current carrying region,” in reference to drain region 236 and source region 238 is not meant to imply that other regions of NLDMOSFET 200 do not carry current. The drift region 232 is formed within a central portion of the active area 230, and extends from the top substrate surface 212 into the substrate 210 to a depth that is less than the depth of NBL 220. The drain region 236 is formed within the drift region 232, and is more heavily doped than the drift region 232. The drain region 236 extends from the top substrate surface 212 into the substrate 210 to a depth significantly less than the depth of the drift region 232. The body region 234 is formed between the drift region 232 and the sinker region 222, and extends from the top substrate surface 212 into the substrate 210 to a depth that is less than the depth of NBL 220, and that may be less than the depth of the drift region 232 (although body region 234 may extend to depths that are substantially equal to or greater than the depth of the drift region 232, as well). In an embodiment, the body region 234 abuts the drift region 232 and is laterally separated from the sinker region 222, as shown in
According to an embodiment, NLDMOSFET 200 may further include various shallow trench isolation (STI) structures 250, 252, 254, as shown in
According to an embodiment, NLDMOSFET 200 further includes a resistor circuit (e.g., resistor circuit 160,
According to an embodiment, and as discussed above, the NLDMOSFET also includes resistive network 346 electrically coupled between the drain region (e.g., drain region 236) and the device's isolation structure. Although a single resistor is used to depict the resistive network 346 in
During normal operation in which the drain potential is elevated, the isolation structure potential closely follows that of the drain region with a voltage drop across resistive network 346 that depends on the amount of current flowing through the isolation structure. On the other hand, when the drain potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across the resistive network 346. By holding up the potential of the isolation structure when the drain potential goes negative, carrier injection into the substrate that may otherwise occur if the drain and isolation structure were merely shorted may be reduced, thus avoiding disruption of adjacent circuit blocks.
According to another embodiment, the resistor circuit (e.g., resistor circuit 160,
Schottky diode 410 and resistive network 446 are electrically coupled in series between the drain region (e.g., drain region 236) and the device's isolation structure. Schottky diode 410 may be formed, for example, by a Schottky contact (not illustrated) in contact with the isolation structure (e.g., with sinker region 222). More particularly, in an embodiment, the Schottky diode may be formed from the metal-semiconductor junction between a Schottky contact (e.g., formed with silicide on the top substrate surface) and the top surface of sinker region 222. In an alternate embodiment, the Schottky contact may be formed on a sidewall or other surface that is not co-planar with the top substrate surface 212.
During operation, when the drain potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across resistive network 446 in series with the reverse breakdown voltage of the Schottky diode 410. For example, referring again to
According to yet another embodiment, the resistor circuit (e.g., resistor circuit 160,
Schottky diode 510 (e.g., the interface between a Schottky contact (not illustrated) and sinker region 222) and resistive network 546 are electrically coupled in parallel between the drain region (e.g., drain region 236) and the device's isolation structure. During operation, when the drain potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across resistive network 546 in parallel with the reverse breakdown voltage of the Schottky diode 510. As with the resistor circuit discussed in conjunction with
In the embodiments discussed in conjunction with
In the embodiments discussed in conjunction with
According to yet another embodiment, a resistor circuit (e.g., resistor circuit 160,
Resistive network 646 and PN junction diode 610 are electrically coupled in series between the drain region (e.g., drain region 236) and the device's isolation structure. During operation, when the drain potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across resistive network 646 in series with the reverse breakdown voltage of the PN junction diode 610. As with the embodiment previously discussed in conjunction with
According to yet another embodiment, the resistor circuit (e.g., resistor circuit 160,
Resistive network 746 and PN junction diode 710 are electrically coupled in parallel between the drain region (e.g., drain region 236) and the device's isolation structure. During operation, when the drain potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across resistive network 746 in parallel with the reverse breakdown voltage of the PN junction diode 710. As with the resistor circuit discussed in conjunction with
In the embodiments discussed in conjunction with
In the embodiments discussed in conjunction with
In the above described embodiments, the drain region and isolation structure of an NLDMOSFET (e.g., NLDMOSFET 112, 200,
PLDMOSFET 800 is formed in and on a P-type semiconductor substrate 810 (e.g., the SOC substrate discussed in conjunction with
PLDMOSFET 800 further includes an active device formed within the active area 830. According to an embodiment, the active device includes a P-type drift region 832, an N-type body region 834, a P-type drain region 836, a P-type source region 838, and a gate electrode 842 (and corresponding gate dielectric, not numbered). The drift region 832 is formed within a central portion of the active area 830, and extends from the top substrate surface 812 into the substrate 810 to a depth that is less than the depth of NBL 820. The drain region 836 is formed within the drift region 832, and is more heavily doped than the drift region 832. The drain region 836 extends from the top substrate surface 812 into the substrate 810 to a depth significantly less than the depth of the drift region 832. A conductive interconnect electrically couples the drain region 836 to a drain terminal 866.
The body region 834 is formed between the drift region 832 and the sinker region 822, and extends from the top substrate surface 812 into the substrate 810 to a depth that is less than the depth of NBL 820, and that may be greater than the depth of the drift region 832 (although body region 834 may extend to depths that are less than or substantially equal to the depth of the drift region 832, as well). In an embodiment, the body region 834 abuts the drift region 832. In addition, the body region 834 is merged with the sinker region 822, in an embodiment, as shown in
According to an embodiment, PLDMOSFET 800 may further include various STI structures 850, 852, as shown in
According to an embodiment, PLDMOSFET 800 further includes a resistor circuit (e.g., resistor circuit 162,
As mentioned above, according to an alternate embodiment, the body region 834 may be laterally separated from the sinker region 822 so that a P-type gap is present between the body region 834 and the sinker region 822. In addition, an STI structure or silicide blocking layer may be included at the substrate surface to ensure isolation between the regions. The P-type gap may be formed from the portion 816 of the P-type substrate within the isolation structure (which would extend to the top substrate surface 812 between the body region 834 and the sinker region 822), or from a P-type well region extending from the top substrate surface 812 and located between the body region 834 and the sinker region 822. In such embodiments, PLDMOSFET 800 may further include an N-type body contact region (not illustrated) formed within the body region 834 (e.g., between the source region 838 and the sinker region 822, where the body contact region may be separated from the source region 838 by an STI structure or silicide blocking layer). The body contact region and the source region 838 may be electrically coupled (shorted) through a conductive interconnect, and the diode circuit may be electrically coupled between the isolation structure (e.g., sinker region 822) and the shorted source and body regions. During normal operation, when the body region 834, source region 838, and isolation structure all are at high potentials, the isolation structure and body region 834 can be effectively shorted through the lateral depletion of the P-type gap between them (e.g., which may be completely depleted before breakdown between them), or through the vertical depletion of the portion 816 of the P-type substrate between the body region 834 and the NBL 820, whichever comes first.
According to an embodiment, and as discussed above, the PLDMOSFET also includes resistive network 946 electrically coupled between the source region (e.g., source region 838) and the device's isolation structure. Although a single resistor is used to depict the resistive network 946 in
During normal operation in which the source potential is elevated, the isolation structure potential closely follows that of the source region with a voltage drop across resistive network 946 that depends on the amount of current flowing through the body region. On the other hand, when the source potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across the resistive network 946. By holding up the potential of the isolation structure when the source potential goes negative, carrier injection into the substrate that may otherwise occur if the source and isolation structure were merely shorted may be reduced, thus avoiding disruption of adjacent circuit blocks.
According to another embodiment, the resistor circuit (e.g., resistor circuit 162,
Schottky diode 1010 and resistive network 1046 are electrically coupled in series between the source region (e.g., source region 838) and the device's isolation structure. Schottky diode 1010 may be formed, for example, by a Schottky contact (not illustrated) in contact with the isolation structure (e.g., with sinker region 822). More particularly, in an embodiment, the Schottky diode may be formed from the metal-semiconductor junction between a Schottky contact (e.g., formed with silicide on the top substrate surface) and the top surface of sinker region 822. In an alternate embodiment, the Schottky contact may be formed on a sidewall or other surface that is not co-planar with the top substrate surface 812.
During operation, when the source potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across resistive network 1046 in series with the reverse breakdown voltage of the Schottky diode 1010. The combination of the Schottky diode 1010 and resistive network 1046 may allow for more flexibility in the construction of the Schottky diode 1010. In addition, in choosing a value for resistive network 1046 to achieve optimum overall results in maintaining the PLDMOSFET's integrity, ESD robustness may be achieved while reducing substrate injection. More specifically, for example, under conditions in which the Schottky diode 1010 is run into breakdown (e.g., during ESD stress), the current through the Schottky diode 1010 is limited by resistive network 1046 to the extent of its capability, thus reducing the likelihood that an ESD event may damage Schottky diode 1010.
According to yet another embodiment, the resistor circuit (e.g., resistor circuit 162,
Schottky diode 1110 (e.g., the interface between a Schottky contact (not illustrated) and sinker region 822) and resistive network 1146 are electrically coupled in parallel between the source region (e.g., source region 838) and the device's isolation structure. During operation, when the source potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across resistive network 1146 in parallel with the reverse breakdown voltage of the Schottky diode 1110. As with the resistor circuit discussed in conjunction with
In the embodiments discussed in conjunction with
In the embodiments discussed in conjunction with
According to yet another embodiment, a resistor circuit (e.g., resistor circuit 162,
Resistive network 1246 and PN junction diode 1210 are electrically coupled in series between the source region (e.g., source region 838) and the device's isolation structure. During operation, when the source potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across resistive network 1246 in series with the reverse breakdown voltage of the PN junction diode 1210. As with the embodiment previously discussed in conjunction with
According to yet another embodiment, the resistor circuit (e.g., resistor circuit 162,
Resistive network 1346 and PN junction diode 1310 are electrically coupled in parallel between the source region (e.g., source region 836) and the device's isolation structure. During operation, when the source potential transitions to a negative voltage, the isolation structure potential is held up by the voltage drop across resistive network 1346 in parallel with the reverse breakdown voltage of the PN junction diode 1310. As with the resistor circuit discussed in conjunction with
In the embodiments discussed in conjunction with
In the embodiments discussed in conjunction with
The method begins, in block 1402, by providing a substrate (e.g., an SOC substrate) having a first conductivity type (e.g., P-type substrate 210, 810). The substrate may include a base substrate and an epitaxial layer grown on the base substrate, for example. An active device (e.g., associated with a driver circuit) may then be formed (blocks 1404, 1406, 1408). For example, in block 1404, an isolation structure may be formed in the substrate. As described in detail previously, the isolation structure may include a buried layer of a second conductivity type (e.g., NBL 220, 820) and a sinker region of the second conductivity type (e.g., sinker region 222, 822) extending from the substrate top surface to the buried layer. The isolation structure formed from the combination of the buried layer and sinker region may substantially surround an active area of the device (e.g., active area 230, 830). In block 1406, an active device may be formed within the active area. For example, among other things, an active device formed in the active area may include a drift region, a body region, a gate, and current carrying regions adjacent opposite ends of a channel region of the device (e.g., a drain region and a source region), as previously described.
In block 1408, a resistor circuit (e.g., resistor circuit 162,
In block 1410, which may be performed in parallel with blocks 1404, 1406, and 1408, “other devices” may be formed in and on the substrate, including forming additional devices associated with a driver circuit (e.g., driver circuit 110,
As discussed previously, the device formed in blocks 1404, 1406, and 1408 is configured to reduce current injection into the SOC substrate under various operating conditions. More particularly, the resistor circuit coupled between a current carrying region (e.g., a drain or source region) and the isolation structure of at least one active device of the driver circuit may result in reduction of injection current, when compared with other systems in which such a resistor circuit is not present (e.g., in systems in which the source region and isolation structure are merely shorted together). Accordingly, the various embodiments may produce significant advantageous results.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist, especially with respect to choices of device types, materials and doping. It should be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the embodiments in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the inventive subject matter as set forth in the appended claims and the legal equivalents thereof.
Claims
1. A semiconductor device, comprising:
- a semiconductor substrate having a first conductivity type and a top substrate surface;
- a buried layer below the top substrate surface, wherein the buried layer has a second conductivity type that is different from the first conductivity type;
- a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity type, and an isolation structure is formed by the sinker region and the buried layer;
- an active device in the semiconductor substrate within a portion of the substrate contained by the isolation structure, wherein the active device includes a current carrying region selected from a source region and a drain region; and
- a resistor circuit connected between the isolation structure and the current carrying region.
2. The semiconductor device of claim 1, wherein the resistor circuit comprises:
- a polycrystalline silicon resistor.
3. The semiconductor device of claim 1, wherein the resistor circuit comprises:
- a first resistive network; and
- a Schottky diode coupled to the first resistive network, wherein the Schottky diode is formed from a Schottky contact coupled with the isolation region.
4. The semiconductor device of claim 3, wherein:
- the Schottky diode is coupled to the first resistive network in series.
5. The semiconductor device of claim 3, wherein:
- the Schottky diode is coupled to the first resistive network in parallel.
6. The semiconductor device of claim 5, wherein the resistor circuit further comprises:
- a second resistive network coupled to the Schottky diode in series.
7. The semiconductor device of claim 3, wherein the resistor circuit further comprises:
- a PN junction diode coupled to the Schottky diode in parallel.
8. The semiconductor device of claim 1, wherein the resistor circuit comprises:
- a first resistive network; and
- a PN junction diode coupled to the first resistive network.
9. The semiconductor device of claim 8, wherein:
- the PN junction diode is coupled to the first resistive network in series.
10. The semiconductor device of claim 8, wherein:
- the PN junction diode is coupled to the first resistive network in parallel.
11. The semiconductor device of claim 10, wherein the resistor circuit further comprises:
- a second resistive network coupled to the PN junction diode in series.
12. The semiconductor device of claim 8, further comprising:
- a further region of the first conductivity type extending into the sinker region, wherein the PN junction diode is formed between the further region and the sinker region.
13. The semiconductor device of claim 8, wherein the PN junction diode comprises a polycrystalline silicon diode.
14. The semiconductor device of claim 1, wherein the current carrying region is a drain region of the active device, and wherein the drain region is of the second conductivity type.
15. The semiconductor device of claim 14, wherein the active device comprises:
- a drift region of the second conductivity type within a central portion of the active area and extending from the top substrate surface into the semiconductor substrate;
- the drain region extending into the drift region from the top substrate surface;
- a body region of the first conductivity type extending from the top substrate surface into the semiconductor substrate between the drift region and the isolation structure;
- a source region of the second conductivity type extending into the body region from the top substrate surface; and
- a body contact region of the first conductivity type within the body region and extending from the top substrate surface into the semiconductor substrate between the source region and the isolation structure.
16. The semiconductor device of claim 1, wherein the current carrying region is a source region of the active device, wherein the source region is of the first conductivity type.
17. The semiconductor device of claim 16, wherein the active device comprises:
- a drift region of the first conductivity type within a central portion of the active area and extending from the top substrate surface into the semiconductor substrate;
- a drain region of the first conductivity type extending into the drift region from the top substrate surface;
- a body region of the second conductivity type extending from the top substrate surface into the semiconductor substrate between the drift region and the isolation structure; and
- the source region extending into the body region from the top substrate surface.
18. A driver circuit comprising:
- a first laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) formed on a semiconductor substrate having a first conductivity type and a top substrate surface, wherein the first LDMOSFET includes a buried layer below the top substrate surface, wherein the buried layer has a second conductivity type that is different from the first conductivity type, a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity type, and an isolation structure is formed by the sinker region and the buried layer, an active device in a portion of the semiconductor substrate contained by the isolation structure, wherein the active device includes a current carrying region; and a resistor circuit connected between the isolation structure and the current carrying region.
19. The driver circuit of claim 18, wherein the resistor circuit comprises:
- a polycrystalline silicon resistor.
20. The driver circuit of claim 18, wherein the resistor circuit comprises:
- a first resistive network; and
- a Schottky diode coupled to the first resistive network, wherein the Schottky diode is formed from a Schottky contact coupled with the isolation region.
21. The driver circuit of claim 20, wherein the Schottky diode is coupled to the first resistive network in parallel, and the resistor circuit further comprises:
- a second resistive network coupled to the Schottky diode in series.
22. The driver circuit of claim 18, wherein the resistor circuit comprises:
- a first resistive network; and
- a PN junction diode coupled to the resistive network.
23. The driver circuit of claim 22, further comprising:
- a further region of the first conductivity type extending into the sinker region, wherein the PN junction diode is formed between the further region and the sinker region.
24. The driver circuit of claim 22, wherein the PN junction diode comprises a polycrystalline silicon diode.
25. The driver circuit of claim 22, wherein the PN junction diode is coupled to the first resistive network in parallel, and the resistor circuit further comprises:
- a second resistive network coupled to the PN junction diode in series.
26. A method for forming a semiconductor device, the method comprising the steps of:
- forming a buried layer below a top substrate surface of a semiconductor substrate having a first conductivity type, wherein the buried layer has a second conductivity type that is different from the first conductivity type;
- forming a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity type, and an isolation structure is formed by the sinker region and the buried layer;
- forming an active device in a portion of the semiconductor substrate contained by the isolation structure, wherein the active device includes a current carrying region; and
- forming a resistor circuit connected between the isolation structure and the current carrying region.
27. The method of claim 26, wherein forming the resistor circuit comprises:
- forming and interconnecting a polycrystalline silicon resistor as part of the resistor circuit.
28. The method of claim 26, wherein the resistor circuit includes a resistive network and a Schottky diode, and forming the resistor circuit comprises:
- forming the resistive network;
- forming the Schottky diode, wherein the Schottky diode includes a Schottky contact coupled with the isolation region; and
- coupling the resistive network to the Schottky contact.
29. The method of claim 26, wherein the resistor circuit includes a resistive network and a PN junction diode, and forming the resistor circuit comprises:
- forming the resistive network;
- forming a further region of the first conductivity type extending into the sinker region, wherein the PN junction diode is formed between the further region and the sinker region; and
- coupling the resistive network to the further region.
30. The method of claim 26, wherein the resistor circuit includes a resistive network and a PN junction diode, and forming the resistor circuit comprises:
- forming the resistive network;
- forming the PN junction diode as a polycrystalline silicon diode; and
- coupling the resistive network to the polycrystalline silicon diode.
Type: Application
Filed: Jun 29, 2012
Publication Date: Jan 2, 2014
Inventors: HUBERT M. BODE (Haar), WEIZE CHEN (Phoenix, AZ), RICHARD J. DE SOUZA (Chandler, AZ), PATRICE M. PARRIS (Phoenix, AZ)
Application Number: 13/538,577
International Classification: H01L 27/06 (20060101); H01L 21/761 (20060101);