Junction field effect voltage reference

- Analog Devices, Inc.

A JFET pair having unequal pinchoff voltages is operated in saturation with equal source-drain current to channel width-to-length ratios to provide a reference voltage output. Positive or negative voltage references can be implemented using either n-channel or p-channel JFETs. The pinchoff voltage difference results from the channel for one JFET having a heavier doping level than that of the other JFET.

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Claims

1. A JFET voltage reference which provides a positive output voltage, comprising:

a pair of JFETs having source, drain and gate terminals, different channel doping densities which result in unequal pinchoff voltages, and equal channel width-to-length ratios, each JFET characterized by a source-drain current path between its respective source and drain terminals,
an operational amplifier having inverting and noninverting inputs and an output, and
a pair of equal current current sources,
the source-drain current paths of said JFETs connected to opposite respective ones of said operational amplifier inputs and also to receive equal currents from said current sources and to establish respective current flow paths between said current sources and a ground reference through respective ones of said JFET source-drain current paths, said current source currents being sufficient to maintain said JFETs in saturation, and the gates of said JFETs connected across a resistor, said resistor being part of a resistance circuit that is connected to the operational amplifier output to reproduce the difference in pinchoff voltages between said JFETs across said resistor and to establish a voltage reference output as a function of the voltage across said resistor.

2. The voltage reference of claim 1, wherein said resistance circuit establishes said voltage reference output at said operational amplifier output.

3. The voltage reference of claim 1, wherein said JFETs are n-channel JFETs.

4. The voltage reference of claim 1, wherein said JFETs are p-channel JFETs.

5. The voltage reference of claim 1, wherein said JFETs have substantially equal gate doping levels.

6. A JFET voltage reference which provides a negative output, comprising:

a pair of JFETs having source, drain and gate terminals, different channel doping densities which result in unequal pinchoff voltages, and equal channel width-to-length ratios, each JFET characterized by a source-drain current path between its respective source and drain terminals,
an operational amplifier having inverting and noninverting inputs and an output, and
a pair of equal current current sources,
the source-drain current paths of said JFETs connected to opposite respective ones of said operational amplifier inputs and also to receive equal currents from said current sources and to establish respective current flow paths between said current sources and a negative voltage supply through respective ones of said JFET source-drain current paths, said current source currents being sufficient to maintain said JFETs in saturation, and the gates of said JFETs connected across a resistor, said resistor being part of a resistance circuit that is connected to the operational amplifier output to reproduce the difference in pinchoff voltages between said JFETs across said resistor and to establish a voltage reference output as a function of the voltage across said resistor.

7. The voltage reference of claim 6, wherein said resistance circuit establishes said voltage reference output at said operational amplifier output.

8. The voltage reference of claim 6, wherein said JFETs are n-channel JFETs.

9. The voltage reference of claim 6, wherein said JFETs are p-channel JFETs.

10. The voltage reference of claim 6, wherein said JFETs have substantially equal gate doping levels.

Referenced Cited
U.S. Patent Documents
4068134 January 10, 1978 Tobey, Jr. et al.
4267501 May 12, 1981 Smith
4357571 November 2, 1982 Roessler
4427903 January 24, 1984 Sugimoto
4654578 March 31, 1987 Salerno et al.
4952821 August 28, 1990 Kokubun
5001484 March 19, 1991 Weiss
5311115 May 10, 1994 Archer
5424663 June 13, 1995 Wong
5596265 January 21, 1997 Wrathal et al.
Other references
  • Fink et al., Ed., Electronics Engineers' Handbook, 3d ed. McGraw Hill Book Co., 1989, pp. 8.48-8.50. Edward S. Yang, Fundamentals of Semiconductor Devices, McGraw Hill Book Company, New York, 1987, pp. 182-195.
Patent History
Patent number: 5838192
Type: Grant
Filed: Jan 17, 1996
Date of Patent: Nov 17, 1998
Assignee: Analog Devices, Inc. (Norwood, MA)
Inventors: Derek F. Bowers (Sunnyvale, CA), Larry C. Tippie (Santa Clara, CA)
Primary Examiner: Terry D. Cunningham
Law Firm: Koppel & Jacobs
Application Number: 8/587,548